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Add 32-bit RISC-V support (#16231)

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Alf-André Walla 2020-12-03 17:33:42 +01:00 • committed by GitHub
commit 545c406cbe
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4 changed files with 7 additions and 4 deletions
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2
compiler/installer.ini
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@ -6,7 +6,7 @@ Name: "Nim"
Version: "$version" Version: "$version"
Platforms: """ Platforms: """
windows: i386;amd64 windows: i386;amd64
linux: i386;hppa;ia64;alpha;amd64;powerpc64;arm;sparc;sparc64;m68k;mips;mipsel;mips64;mips64el;powerpc;powerpc64el;arm64;riscv64 linux: i386;hppa;ia64;alpha;amd64;powerpc64;arm;sparc;sparc64;m68k;mips;mipsel;mips64;mips64el;powerpc;powerpc64el;arm64;riscv32;riscv64
macosx: i386;amd64;powerpc64 macosx: i386;amd64;powerpc64
solaris: i386;amd64;sparc;sparc64 solaris: i386;amd64;sparc;sparc64
freebsd: i386;amd64;powerpc64;arm;arm64;riscv64;sparc64;mips;mipsel;mips64;mips64el;powerpc;powerpc64el freebsd: i386;amd64;powerpc64;arm;arm64;riscv64;sparc64;mips;mipsel;mips64;mips64el;powerpc;powerpc64el

3
compiler/platform.nim
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@ -193,7 +193,7 @@ type
cpuNone, cpuI386, cpuM68k, cpuAlpha, cpuPowerpc, cpuPowerpc64, cpuNone, cpuI386, cpuM68k, cpuAlpha, cpuPowerpc, cpuPowerpc64,
cpuPowerpc64el, cpuSparc, cpuVm, cpuHppa, cpuIa64, cpuAmd64, cpuMips, cpuPowerpc64el, cpuSparc, cpuVm, cpuHppa, cpuIa64, cpuAmd64, cpuMips,
cpuMipsel, cpuArm, cpuArm64, cpuJS, cpuNimVM, cpuAVR, cpuMSP430, cpuMipsel, cpuArm, cpuArm64, cpuJS, cpuNimVM, cpuAVR, cpuMSP430,
cpuSparc64, cpuMips64, cpuMips64el, cpuRiscV64, cpuEsp, cpuWasm32 cpuSparc64, cpuMips64, cpuMips64el, cpuRiscV32, cpuRiscV64, cpuEsp, cpuWasm32
type type
TEndian* = enum TEndian* = enum
@ -226,6 +226,7 @@ const
(name: "sparc64", intSize: 64, endian: bigEndian, floatSize: 64, bit: 64), (name: "sparc64", intSize: 64, endian: bigEndian, floatSize: 64, bit: 64),
(name: "mips64", intSize: 64, endian: bigEndian, floatSize: 64, bit: 64), (name: "mips64", intSize: 64, endian: bigEndian, floatSize: 64, bit: 64),
(name: "mips64el", intSize: 64, endian: littleEndian, floatSize: 64, bit: 64), (name: "mips64el", intSize: 64, endian: littleEndian, floatSize: 64, bit: 64),
(name: "riscv32", intSize: 32, endian: littleEndian, floatSize: 64, bit: 32),
(name: "riscv64", intSize: 64, endian: littleEndian, floatSize: 64, bit: 64), (name: "riscv64", intSize: 64, endian: littleEndian, floatSize: 64, bit: 64),
(name: "esp", intSize: 32, endian: littleEndian, floatSize: 64, bit: 32), (name: "esp", intSize: 32, endian: littleEndian, floatSize: 64, bit: 32),
(name: "wasm32", intSize: 32, endian: littleEndian, floatSize: 64, bit: 32)] (name: "wasm32", intSize: 32, endian: littleEndian, floatSize: 64, bit: 32)]

2
lib/system.nim
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@ -1068,7 +1068,7 @@ const
## Possible values: ## Possible values:
## `"i386"`, `"alpha"`, `"powerpc"`, `"powerpc64"`, `"powerpc64el"`, ## `"i386"`, `"alpha"`, `"powerpc"`, `"powerpc64"`, `"powerpc64el"`,
## `"sparc"`, `"amd64"`, `"mips"`, `"mipsel"`, `"arm"`, `"arm64"`, ## `"sparc"`, `"amd64"`, `"mips"`, `"mipsel"`, `"arm"`, `"arm64"`,
## `"mips64"`, `"mips64el"`, `"riscv64"`. ## `"mips64"`, `"mips64el"`, `"riscv32"`, `"riscv64"`.
seqShallowFlag = low(int) seqShallowFlag = low(int)
strlitFlag = 1 shl (sizeof(int)*8 - 2) # later versions of the codegen \ strlitFlag = 1 shl (sizeof(int)*8 - 2) # later versions of the codegen \

4
lib/system/platforms.nim
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@ -33,7 +33,8 @@ type
vm, ## Some Virtual machine: Nim's VM or JavaScript vm, ## Some Virtual machine: Nim's VM or JavaScript
avr, ## AVR based processor avr, ## AVR based processor
msp430, ## TI MSP430 microcontroller msp430, ## TI MSP430 microcontroller
riscv64 ## RISC-V 64-bit processor riscv32, ## RISC-V 32-bit processor
riscv64, ## RISC-V 64-bit processor
wasm32 ## WASM, 32-bit wasm32 ## WASM, 32-bit
OsPlatform* {.pure.} = enum ## the OS this program will run on. OsPlatform* {.pure.} = enum ## the OS this program will run on.
@ -91,6 +92,7 @@ const
elif defined(vm): CpuPlatform.vm elif defined(vm): CpuPlatform.vm
elif defined(avr): CpuPlatform.avr elif defined(avr): CpuPlatform.avr
elif defined(msp430): CpuPlatform.msp430 elif defined(msp430): CpuPlatform.msp430
elif defined(riscv32): CpuPlatform.riscv32
elif defined(riscv64): CpuPlatform.riscv64 elif defined(riscv64): CpuPlatform.riscv64
elif defined(wasm32): CpuPlatform.wasm32 elif defined(wasm32): CpuPlatform.wasm32
else: CpuPlatform.none else: CpuPlatform.none