parent
03fa9a9041
commit
56a00da34a
2 changed files with 17 additions and 6 deletions
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@ -220,9 +220,9 @@ proc getFreeRegister(cc: PCtx; k: TSlotKind; start: int): TRegister =
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return TRegister(i)
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return TRegister(i)
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if c.maxSlots >= high(TRegister):
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if c.maxSlots >= high(TRegister):
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globalError(cc.config, cc.bestEffort, "VM problem: too many registers required")
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globalError(cc.config, cc.bestEffort, "VM problem: too many registers required")
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result = TRegister(c.maxSlots)
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result = TRegister(max(c.maxSlots, start))
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c.slots[c.maxSlots] = (inUse: true, kind: k)
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c.slots[result] = (inUse: true, kind: k)
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inc c.maxSlots
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c.maxSlots = result + 1
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proc getTemp(cc: PCtx; tt: PType): TRegister =
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proc getTemp(cc: PCtx; tt: PType): TRegister =
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let typ = tt.skipTypesOrNil({tyStatic})
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let typ = tt.skipTypesOrNil({tyStatic})
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@ -1483,7 +1483,10 @@ proc checkCanEval(c: PCtx; n: PNode) =
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if {sfCompileTime, sfGlobal} <= s.flags: return
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if {sfCompileTime, sfGlobal} <= s.flags: return
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if s.kind in {skVar, skTemp, skLet, skParam, skResult} and
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if s.kind in {skVar, skTemp, skLet, skParam, skResult} and
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not s.isOwnedBy(c.prc.sym) and s.owner != c.module and c.mode != emRepl:
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not s.isOwnedBy(c.prc.sym) and s.owner != c.module and c.mode != emRepl:
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cannotEval(c, n)
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# little hack ahead for bug #12612: assume gensym'ed variables
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# are in the right scope:
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if sfGenSym in s.flags and c.prc.sym == nil: discard
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else: cannotEval(c, n)
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elif s.kind in {skProc, skFunc, skConverter, skMethod,
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elif s.kind in {skProc, skFunc, skConverter, skMethod,
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skIterator} and sfForward in s.flags:
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skIterator} and sfForward in s.flags:
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cannotEval(c, n)
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cannotEval(c, n)
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@ -1558,7 +1561,7 @@ proc genAsgn(c: PCtx; le, ri: PNode; requiresCopy: bool) =
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else:
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else:
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if s.kind == skForVar: c.setSlot s
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if s.kind == skForVar: c.setSlot s
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internalAssert c.config, s.position > 0 or (s.position == 0 and
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internalAssert c.config, s.position > 0 or (s.position == 0 and
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s.kind in {skParam,skResult})
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s.kind in {skParam, skResult})
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var dest: TRegister = s.position + ord(s.kind == skParam)
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var dest: TRegister = s.position + ord(s.kind == skParam)
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assert le.typ != nil
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assert le.typ != nil
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if needsAdditionalCopy(le) and s.kind in {skResult, skVar, skParam}:
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if needsAdditionalCopy(le) and s.kind in {skResult, skVar, skParam}:
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@ -1638,7 +1641,7 @@ proc genRdVar(c: PCtx; n: PNode; dest: var TDest; flags: TGenFlags) =
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else:
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else:
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if s.kind == skForVar and c.mode == emRepl: c.setSlot(s)
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if s.kind == skForVar and c.mode == emRepl: c.setSlot(s)
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if s.position > 0 or (s.position == 0 and
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if s.position > 0 or (s.position == 0 and
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s.kind in {skParam,skResult}):
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s.kind in {skParam, skResult}):
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if dest < 0:
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if dest < 0:
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dest = s.position + ord(s.kind == skParam)
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dest = s.position + ord(s.kind == skParam)
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internalAssert(c.config, c.prc.slots[dest].kind < slotSomeTemp)
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internalAssert(c.config, c.prc.slots[dest].kind < slotSomeTemp)
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@ -134,6 +134,14 @@ doAssert fmt"{nat:3o}" == "100"
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doAssert fmt"{nat:3x}" == " 40"
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doAssert fmt"{nat:3x}" == " 40"
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doAssert fmt"{nat:3X}" == " 40"
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doAssert fmt"{nat:3X}" == " 40"
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# bug #12612
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proc my_proc =
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const value = "value"
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const a = &"{value}"
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assert a == value
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my_proc()
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block:
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block:
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template fmt(pattern: string; openCloseChar: char): untyped =
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template fmt(pattern: string; openCloseChar: char): untyped =
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fmt(pattern, openCloseChar, openCloseChar)
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fmt(pattern, openCloseChar, openCloseChar)
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