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improve cache line size (#17885)

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* improve cache line size

- 64bit system tend to use cache line of 64 bytes
- add align

https://trishagee.com/2011/07/22/dissecting_the_disruptor_why_its_so_fast_part_two__magic_cache_line_padding


Though I'm not sure, what do you think? @timotheecour

* Update lib/pure/concurrency/threadpool.nim
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flywind 2021-04-29 19:39:36 +08:00 • committed by GitHub
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lib/pure/concurrency/threadpool.nim
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@ -52,17 +52,14 @@ proc signal(cv: var Semaphore) =
release(cv.L) release(cv.L)
signal(cv.c) signal(cv.c)
const CacheLineSize = 32 # true for most archs const CacheLineSize = 64 # true for most archs
type type
Barrier {.compilerproc.} = object Barrier {.compilerproc.} = object
entered: int entered: int
cv: Semaphore # Semaphore takes 3 words at least cv: Semaphore # Semaphore takes 3 words at least
when sizeof(int) < 8: left {.align(CacheLineSize).}: int
cacheAlign: array[CacheLineSize-4*sizeof(int), byte] interest {.align(CacheLineSize).} : bool # whether the master is interested in the "all done" event
left: int
cacheAlign2: array[CacheLineSize-sizeof(int), byte]
interest: bool # whether the master is interested in the "all done" event
proc barrierEnter(b: ptr Barrier) {.compilerproc, inline.} = proc barrierEnter(b: ptr Barrier) {.compilerproc, inline.} =
# due to the signaling between threads, it is ensured we are the only # due to the signaling between threads, it is ensured we are the only