vm2: new representation of registers

This commit is contained in:
Araq 2014-02-21 17:23:37 +01:00
commit 6e584c42c2
9 changed files with 568 additions and 534 deletions

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@ -8,7 +8,7 @@
#
## This module contains the type definitions for the new evaluation engine.
## An instruction is 1-2 int32s in memory, it is a register based VM.
## An instruction is 1-3 int32s in memory, it is a register based VM.
import ast, passes, msgs, intsets
@ -32,17 +32,17 @@ type
opcAsgnFloat,
opcAsgnRef,
opcAsgnComplex,
opcRegToNode,
opcNodeToReg,
opcLdArr, # a = b[c]
opcLdArrRef,
opcWrArr, # a[b] = c
opcWrArrRef,
opcLdObj, # a = b.c
opcLdObjRef,
opcWrObj, # a.b = c
opcWrObjRef,
opcAddr,
opcDeref,
opcAddrReg,
opcAddrNode,
opcLdDeref,
opcWrDeref,
opcWrStrIdx,
opcLdStrIdx, # a = b[c]
@ -117,15 +117,13 @@ type
opcNew,
opcNewSeq,
opcLdNull, # dest = nullvalue(types[Bx])
opcLdNullReg,
opcLdConst, # dest = constants[Bx]
opcAsgnConst, # dest = copy(constants[Bx])
opcLdGlobal, # dest = globals[Bx]
opcLdImmInt, # dest = immediate value
opcNBindSym,
opcWrGlobal,
opcWrGlobalRef,
opcGlobalAlias, # load an alias to a global into a register
opcGlobalOnce, # used to introduce an assignment to a global once
opcSetType, # dest.typ = types[Bx]
opcTypeTrait