parent
8407a57499
commit
afbcd1b330
34 changed files with 530 additions and 314 deletions
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@ -16,7 +16,7 @@ import
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strutils, msgs, vmdef, vmgen, nimsets, types, passes,
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parser, vmdeps, idents, trees, renderer, options, transf, parseutils,
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vmmarshal, gorgeimpl, lineinfos, tables, btrees, macrocacheimpl,
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modulegraphs, sighashes
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modulegraphs, sighashes, int128
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from semfold import leValueConv, ordinalValToString
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from evaltempl import evalTemplate
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@ -411,7 +411,7 @@ proc opConv(c: PCtx; dest: var TFullReg, src: TFullReg, desttyp, srctyp: PType):
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dest.intVal = int(src.floatVal)
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else:
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dest.intVal = src.intVal
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if dest.intVal < firstOrd(c.config, desttyp) or dest.intVal > lastOrd(c.config, desttyp):
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if toInt128(dest.intVal) < firstOrd(c.config, desttyp) or toInt128(dest.intVal) > lastOrd(c.config, desttyp):
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return true
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of tyUInt..tyUInt64:
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if dest.kind != rkInt:
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@ -1312,7 +1312,7 @@ proc rawExecute(c: PCtx, start: int, tos: PStackFrame): TFullReg =
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of opcQuit:
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if c.mode in {emRepl, emStaticExpr, emStaticStmt}:
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message(c.config, c.debug[pc], hintQuitCalled)
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msgQuit(int8(getOrdValue(regs[ra].regToNode)))
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msgQuit(int8(toInt(getOrdValue(regs[ra].regToNode))))
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else:
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return TFullReg(kind: rkNone)
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of opcSetLenStr:
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