VM: fixes register leaks [backport] (#12510)
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1 changed files with 2 additions and 0 deletions
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@ -1443,6 +1443,7 @@ proc genDeref(c: PCtx, n: PNode, dest: var TDest, flags: TGenFlags) =
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assert n.typ != nil
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if {gfNodeAddr, gfNode} * flags == {} and fitsRegister(n.typ):
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c.gABC(n, opcNodeToReg, dest, dest)
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c.freeTemp(tmp)
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proc genAsgn(c: PCtx; dest: TDest; ri: PNode; requiresCopy: bool) =
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let tmp = c.genx(ri)
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@ -1532,6 +1533,7 @@ proc genAsgn(c: PCtx; le, ri: PNode; requiresCopy: bool) =
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c.preventFalseAlias(le, opcWrObj, dest, idx, tmp)
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c.freeTemp(idx)
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c.freeTemp(tmp)
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c.freeTemp(dest)
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of nkDerefExpr, nkHiddenDeref:
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let dest = c.genx(le.sons[0], {gfNode})
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let tmp = c.genx(ri)
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