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VM: fixes register leaks [backport] (#12510)

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Andreas Rumpf 2019-10-25 00:45:06 +02:00 • committed by GitHub
commit e0d13abaff
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compiler/vmgen.nim
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@ -1443,6 +1443,7 @@ proc genDeref(c: PCtx, n: PNode, dest: var TDest, flags: TGenFlags) =
assert n.typ != nil assert n.typ != nil
if {gfNodeAddr, gfNode} * flags == {} and fitsRegister(n.typ): if {gfNodeAddr, gfNode} * flags == {} and fitsRegister(n.typ):
c.gABC(n, opcNodeToReg, dest, dest) c.gABC(n, opcNodeToReg, dest, dest)
c.freeTemp(tmp)
proc genAsgn(c: PCtx; dest: TDest; ri: PNode; requiresCopy: bool) = proc genAsgn(c: PCtx; dest: TDest; ri: PNode; requiresCopy: bool) =
let tmp = c.genx(ri) let tmp = c.genx(ri)
@ -1532,6 +1533,7 @@ proc genAsgn(c: PCtx; le, ri: PNode; requiresCopy: bool) =
c.preventFalseAlias(le, opcWrObj, dest, idx, tmp) c.preventFalseAlias(le, opcWrObj, dest, idx, tmp)
c.freeTemp(idx) c.freeTemp(idx)
c.freeTemp(tmp) c.freeTemp(tmp)
c.freeTemp(dest)
of nkDerefExpr, nkHiddenDeref: of nkDerefExpr, nkHiddenDeref:
let dest = c.genx(le.sons[0], {gfNode}) let dest = c.genx(le.sons[0], {gfNode})
let tmp = c.genx(ri) let tmp = c.genx(ri)