jyapayne/ace
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Revert "Added VHDL syntax highlighting, and example code. issue #1642"

Browse source 
This reverts commit 56a37a4053.
This commit is contained in:
OpenShift guest 2013-10-17 00:37:16 -04:00
commit 9fd726a81c
1 changed files with 0 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

1
lib/ace/ext/modelist.js
View file

@ -140,7 +140,6 @@ var supportedModes = {
VBScript: ["vbs"], VBScript: ["vbs"],
Velocity: ["vm"], Velocity: ["vm"],
Verilog: ["v|vh|sv|svh"], Verilog: ["v|vh|sv|svh"],
VHDL: ["vhd|vhdl"],
XML: ["xml|rdf|rss|wsdl|xslt|atom|mathml|mml|xul|xbl"], XML: ["xml|rdf|rss|wsdl|xslt|atom|mathml|mml|xul|xbl"],
XQuery: ["xq"], XQuery: ["xq"],
YAML: ["yaml|yml"] YAML: ["yaml|yml"]