From 75161701a14fb04135c6bc78d0fdaf17dd4212ef Mon Sep 17 00:00:00 2001 From: "mdevan.foobar" Date: Thu, 19 Feb 2009 12:00:28 +0000 Subject: [PATCH] Updated intrinsic ids. git-svn-id: http://llvm-py.googlecode.com/svn/trunk@61 8d1e9007-1d4e-0410-b67e-1979fd6579aa --- llvm/core.py | 1178 +++++++++++++++++++++++----------------------- tools/intrgen.py | 32 ++ 2 files changed, 628 insertions(+), 582 deletions(-) create mode 100755 tools/intrgen.py diff --git a/llvm/core.py b/llvm/core.py index 46b1cc0..59db453 100644 --- a/llvm/core.py +++ b/llvm/core.py @@ -173,588 +173,602 @@ INTR_ATOMIC_LOAD_UMIN = 13 INTR_ATOMIC_LOAD_XOR = 14 INTR_ATOMIC_SWAP = 15 INTR_BSWAP = 16 -INTR_COS = 17 -INTR_CTLZ = 18 -INTR_CTPOP = 19 -INTR_CTTZ = 20 -INTR_DBG_DECLARE = 21 -INTR_DBG_FUNC_START = 22 -INTR_DBG_REGION_END = 23 -INTR_DBG_REGION_START = 24 -INTR_DBG_STOPPOINT = 25 -INTR_EH_DWARF_CFA = 26 -INTR_EH_EXCEPTION = 27 -INTR_EH_RETURN_I32 = 28 -INTR_EH_RETURN_I64 = 29 -INTR_EH_SELECTOR_I32 = 30 -INTR_EH_SELECTOR_I64 = 31 -INTR_EH_TYPEID_FOR_I32 = 32 -INTR_EH_TYPEID_FOR_I64 = 33 -INTR_EH_UNWIND_INIT = 34 -INTR_EXP = 35 -INTR_EXP2 = 36 -INTR_FLT_ROUNDS = 37 -INTR_FRAMEADDRESS = 38 -INTR_GCREAD = 39 -INTR_GCROOT = 40 -INTR_GCWRITE = 41 -INTR_INIT_TRAMPOLINE = 42 -INTR_LOG = 43 -INTR_LOG10 = 44 -INTR_LOG2 = 45 -INTR_LONGJMP = 46 -INTR_MEMCPY_I32 = 47 -INTR_MEMCPY_I64 = 48 -INTR_MEMMOVE_I32 = 49 -INTR_MEMMOVE_I64 = 50 -INTR_MEMORY_BARRIER = 51 -INTR_MEMSET_I32 = 52 -INTR_MEMSET_I64 = 53 -INTR_PART_SELECT = 54 -INTR_PART_SET = 55 -INTR_PCMARKER = 56 -INTR_POW = 57 -INTR_POWI = 58 -INTR_PPC_ALTIVEC_DSS = 59 -INTR_PPC_ALTIVEC_DSSALL = 60 -INTR_PPC_ALTIVEC_DST = 61 -INTR_PPC_ALTIVEC_DSTST = 62 -INTR_PPC_ALTIVEC_DSTSTT = 63 -INTR_PPC_ALTIVEC_DSTT = 64 -INTR_PPC_ALTIVEC_LVEBX = 65 -INTR_PPC_ALTIVEC_LVEHX = 66 -INTR_PPC_ALTIVEC_LVEWX = 67 -INTR_PPC_ALTIVEC_LVSL = 68 -INTR_PPC_ALTIVEC_LVSR = 69 -INTR_PPC_ALTIVEC_LVX = 70 -INTR_PPC_ALTIVEC_LVXL = 71 -INTR_PPC_ALTIVEC_MFVSCR = 72 -INTR_PPC_ALTIVEC_MTVSCR = 73 -INTR_PPC_ALTIVEC_STVEBX = 74 -INTR_PPC_ALTIVEC_STVEHX = 75 -INTR_PPC_ALTIVEC_STVEWX = 76 -INTR_PPC_ALTIVEC_STVX = 77 -INTR_PPC_ALTIVEC_STVXL = 78 -INTR_PPC_ALTIVEC_VADDCUW = 79 -INTR_PPC_ALTIVEC_VADDSBS = 80 -INTR_PPC_ALTIVEC_VADDSHS = 81 -INTR_PPC_ALTIVEC_VADDSWS = 82 -INTR_PPC_ALTIVEC_VADDUBS = 83 -INTR_PPC_ALTIVEC_VADDUHS = 84 -INTR_PPC_ALTIVEC_VADDUWS = 85 -INTR_PPC_ALTIVEC_VAVGSB = 86 -INTR_PPC_ALTIVEC_VAVGSH = 87 -INTR_PPC_ALTIVEC_VAVGSW = 88 -INTR_PPC_ALTIVEC_VAVGUB = 89 -INTR_PPC_ALTIVEC_VAVGUH = 90 -INTR_PPC_ALTIVEC_VAVGUW = 91 -INTR_PPC_ALTIVEC_VCFSX = 92 -INTR_PPC_ALTIVEC_VCFUX = 93 -INTR_PPC_ALTIVEC_VCMPBFP = 94 -INTR_PPC_ALTIVEC_VCMPBFP_P = 95 -INTR_PPC_ALTIVEC_VCMPEQFP = 96 -INTR_PPC_ALTIVEC_VCMPEQFP_P = 97 -INTR_PPC_ALTIVEC_VCMPEQUB = 98 -INTR_PPC_ALTIVEC_VCMPEQUB_P = 99 -INTR_PPC_ALTIVEC_VCMPEQUH = 100 -INTR_PPC_ALTIVEC_VCMPEQUH_P = 101 -INTR_PPC_ALTIVEC_VCMPEQUW = 102 -INTR_PPC_ALTIVEC_VCMPEQUW_P = 103 -INTR_PPC_ALTIVEC_VCMPGEFP = 104 -INTR_PPC_ALTIVEC_VCMPGEFP_P = 105 -INTR_PPC_ALTIVEC_VCMPGTFP = 106 -INTR_PPC_ALTIVEC_VCMPGTFP_P = 107 -INTR_PPC_ALTIVEC_VCMPGTSB = 108 -INTR_PPC_ALTIVEC_VCMPGTSB_P = 109 -INTR_PPC_ALTIVEC_VCMPGTSH = 110 -INTR_PPC_ALTIVEC_VCMPGTSH_P = 111 -INTR_PPC_ALTIVEC_VCMPGTSW = 112 -INTR_PPC_ALTIVEC_VCMPGTSW_P = 113 -INTR_PPC_ALTIVEC_VCMPGTUB = 114 -INTR_PPC_ALTIVEC_VCMPGTUB_P = 115 -INTR_PPC_ALTIVEC_VCMPGTUH = 116 -INTR_PPC_ALTIVEC_VCMPGTUH_P = 117 -INTR_PPC_ALTIVEC_VCMPGTUW = 118 -INTR_PPC_ALTIVEC_VCMPGTUW_P = 119 -INTR_PPC_ALTIVEC_VCTSXS = 120 -INTR_PPC_ALTIVEC_VCTUXS = 121 -INTR_PPC_ALTIVEC_VEXPTEFP = 122 -INTR_PPC_ALTIVEC_VLOGEFP = 123 -INTR_PPC_ALTIVEC_VMADDFP = 124 -INTR_PPC_ALTIVEC_VMAXFP = 125 -INTR_PPC_ALTIVEC_VMAXSB = 126 -INTR_PPC_ALTIVEC_VMAXSH = 127 -INTR_PPC_ALTIVEC_VMAXSW = 128 -INTR_PPC_ALTIVEC_VMAXUB = 129 -INTR_PPC_ALTIVEC_VMAXUH = 130 -INTR_PPC_ALTIVEC_VMAXUW = 131 -INTR_PPC_ALTIVEC_VMHADDSHS = 132 -INTR_PPC_ALTIVEC_VMHRADDSHS = 133 -INTR_PPC_ALTIVEC_VMINFP = 134 -INTR_PPC_ALTIVEC_VMINSB = 135 -INTR_PPC_ALTIVEC_VMINSH = 136 -INTR_PPC_ALTIVEC_VMINSW = 137 -INTR_PPC_ALTIVEC_VMINUB = 138 -INTR_PPC_ALTIVEC_VMINUH = 139 -INTR_PPC_ALTIVEC_VMINUW = 140 -INTR_PPC_ALTIVEC_VMLADDUHM = 141 -INTR_PPC_ALTIVEC_VMSUMMBM = 142 -INTR_PPC_ALTIVEC_VMSUMSHM = 143 -INTR_PPC_ALTIVEC_VMSUMSHS = 144 -INTR_PPC_ALTIVEC_VMSUMUBM = 145 -INTR_PPC_ALTIVEC_VMSUMUHM = 146 -INTR_PPC_ALTIVEC_VMSUMUHS = 147 -INTR_PPC_ALTIVEC_VMULESB = 148 -INTR_PPC_ALTIVEC_VMULESH = 149 -INTR_PPC_ALTIVEC_VMULEUB = 150 -INTR_PPC_ALTIVEC_VMULEUH = 151 -INTR_PPC_ALTIVEC_VMULOSB = 152 -INTR_PPC_ALTIVEC_VMULOSH = 153 -INTR_PPC_ALTIVEC_VMULOUB = 154 -INTR_PPC_ALTIVEC_VMULOUH = 155 -INTR_PPC_ALTIVEC_VNMSUBFP = 156 -INTR_PPC_ALTIVEC_VPERM = 157 -INTR_PPC_ALTIVEC_VPKPX = 158 -INTR_PPC_ALTIVEC_VPKSHSS = 159 -INTR_PPC_ALTIVEC_VPKSHUS = 160 -INTR_PPC_ALTIVEC_VPKSWSS = 161 -INTR_PPC_ALTIVEC_VPKSWUS = 162 -INTR_PPC_ALTIVEC_VPKUHUS = 163 -INTR_PPC_ALTIVEC_VPKUWUS = 164 -INTR_PPC_ALTIVEC_VREFP = 165 -INTR_PPC_ALTIVEC_VRFIM = 166 -INTR_PPC_ALTIVEC_VRFIN = 167 -INTR_PPC_ALTIVEC_VRFIP = 168 -INTR_PPC_ALTIVEC_VRFIZ = 169 -INTR_PPC_ALTIVEC_VRLB = 170 -INTR_PPC_ALTIVEC_VRLH = 171 -INTR_PPC_ALTIVEC_VRLW = 172 -INTR_PPC_ALTIVEC_VRSQRTEFP = 173 -INTR_PPC_ALTIVEC_VSEL = 174 -INTR_PPC_ALTIVEC_VSL = 175 -INTR_PPC_ALTIVEC_VSLB = 176 -INTR_PPC_ALTIVEC_VSLH = 177 -INTR_PPC_ALTIVEC_VSLO = 178 -INTR_PPC_ALTIVEC_VSLW = 179 -INTR_PPC_ALTIVEC_VSR = 180 -INTR_PPC_ALTIVEC_VSRAB = 181 -INTR_PPC_ALTIVEC_VSRAH = 182 -INTR_PPC_ALTIVEC_VSRAW = 183 -INTR_PPC_ALTIVEC_VSRB = 184 -INTR_PPC_ALTIVEC_VSRH = 185 -INTR_PPC_ALTIVEC_VSRO = 186 -INTR_PPC_ALTIVEC_VSRW = 187 -INTR_PPC_ALTIVEC_VSUBCUW = 188 -INTR_PPC_ALTIVEC_VSUBSBS = 189 -INTR_PPC_ALTIVEC_VSUBSHS = 190 -INTR_PPC_ALTIVEC_VSUBSWS = 191 -INTR_PPC_ALTIVEC_VSUBUBS = 192 -INTR_PPC_ALTIVEC_VSUBUHS = 193 -INTR_PPC_ALTIVEC_VSUBUWS = 194 -INTR_PPC_ALTIVEC_VSUM2SWS = 195 -INTR_PPC_ALTIVEC_VSUM4SBS = 196 -INTR_PPC_ALTIVEC_VSUM4SHS = 197 -INTR_PPC_ALTIVEC_VSUM4UBS = 198 -INTR_PPC_ALTIVEC_VSUMSWS = 199 -INTR_PPC_ALTIVEC_VUPKHPX = 200 -INTR_PPC_ALTIVEC_VUPKHSB = 201 -INTR_PPC_ALTIVEC_VUPKHSH = 202 -INTR_PPC_ALTIVEC_VUPKLPX = 203 -INTR_PPC_ALTIVEC_VUPKLSB = 204 -INTR_PPC_ALTIVEC_VUPKLSH = 205 -INTR_PPC_DCBA = 206 -INTR_PPC_DCBF = 207 -INTR_PPC_DCBI = 208 -INTR_PPC_DCBST = 209 -INTR_PPC_DCBT = 210 -INTR_PPC_DCBTST = 211 -INTR_PPC_DCBZ = 212 -INTR_PPC_DCBZL = 213 -INTR_PPC_SYNC = 214 -INTR_PREFETCH = 215 -INTR_READCYCLECOUNTER = 216 -INTR_RETURNADDRESS = 217 -INTR_SETJMP = 218 -INTR_SIGLONGJMP = 219 -INTR_SIGSETJMP = 220 -INTR_SIN = 221 -INTR_SPU_SI_A = 222 -INTR_SPU_SI_ADDX = 223 -INTR_SPU_SI_AH = 224 -INTR_SPU_SI_AHI = 225 -INTR_SPU_SI_AI = 226 -INTR_SPU_SI_AND = 227 -INTR_SPU_SI_ANDBI = 228 -INTR_SPU_SI_ANDC = 229 -INTR_SPU_SI_ANDHI = 230 -INTR_SPU_SI_ANDI = 231 -INTR_SPU_SI_BG = 232 -INTR_SPU_SI_BGX = 233 -INTR_SPU_SI_CEQ = 234 -INTR_SPU_SI_CEQB = 235 -INTR_SPU_SI_CEQBI = 236 -INTR_SPU_SI_CEQH = 237 -INTR_SPU_SI_CEQHI = 238 -INTR_SPU_SI_CEQI = 239 -INTR_SPU_SI_CG = 240 -INTR_SPU_SI_CGT = 241 -INTR_SPU_SI_CGTB = 242 -INTR_SPU_SI_CGTBI = 243 -INTR_SPU_SI_CGTH = 244 -INTR_SPU_SI_CGTHI = 245 -INTR_SPU_SI_CGTI = 246 -INTR_SPU_SI_CGX = 247 -INTR_SPU_SI_CLGT = 248 -INTR_SPU_SI_CLGTB = 249 -INTR_SPU_SI_CLGTBI = 250 -INTR_SPU_SI_CLGTH = 251 -INTR_SPU_SI_CLGTHI = 252 -INTR_SPU_SI_CLGTI = 253 -INTR_SPU_SI_DFA = 254 -INTR_SPU_SI_DFM = 255 -INTR_SPU_SI_DFMA = 256 -INTR_SPU_SI_DFMS = 257 -INTR_SPU_SI_DFNMA = 258 -INTR_SPU_SI_DFNMS = 259 -INTR_SPU_SI_DFS = 260 -INTR_SPU_SI_FA = 261 -INTR_SPU_SI_FCEQ = 262 -INTR_SPU_SI_FCGT = 263 -INTR_SPU_SI_FCMEQ = 264 -INTR_SPU_SI_FCMGT = 265 -INTR_SPU_SI_FM = 266 -INTR_SPU_SI_FMA = 267 -INTR_SPU_SI_FMS = 268 -INTR_SPU_SI_FNMS = 269 -INTR_SPU_SI_FS = 270 -INTR_SPU_SI_FSMBI = 271 -INTR_SPU_SI_MPY = 272 -INTR_SPU_SI_MPYA = 273 -INTR_SPU_SI_MPYH = 274 -INTR_SPU_SI_MPYHH = 275 -INTR_SPU_SI_MPYHHA = 276 -INTR_SPU_SI_MPYHHAU = 277 -INTR_SPU_SI_MPYHHU = 278 -INTR_SPU_SI_MPYI = 279 -INTR_SPU_SI_MPYS = 280 -INTR_SPU_SI_MPYU = 281 -INTR_SPU_SI_MPYUI = 282 -INTR_SPU_SI_NAND = 283 -INTR_SPU_SI_NOR = 284 -INTR_SPU_SI_OR = 285 -INTR_SPU_SI_ORBI = 286 -INTR_SPU_SI_ORC = 287 -INTR_SPU_SI_ORHI = 288 -INTR_SPU_SI_ORI = 289 -INTR_SPU_SI_SF = 290 -INTR_SPU_SI_SFH = 291 -INTR_SPU_SI_SFHI = 292 -INTR_SPU_SI_SFI = 293 -INTR_SPU_SI_SFX = 294 -INTR_SPU_SI_SHLI = 295 -INTR_SPU_SI_SHLQBI = 296 -INTR_SPU_SI_SHLQBII = 297 -INTR_SPU_SI_SHLQBY = 298 -INTR_SPU_SI_SHLQBYI = 299 -INTR_SPU_SI_XOR = 300 -INTR_SPU_SI_XORBI = 301 -INTR_SPU_SI_XORHI = 302 -INTR_SPU_SI_XORI = 303 -INTR_SQRT = 304 -INTR_STACKRESTORE = 305 -INTR_STACKSAVE = 306 -INTR_TRAP = 307 -INTR_VACOPY = 308 -INTR_VAEND = 309 -INTR_VAR_ANNOTATION = 310 -INTR_VASTART = 311 -INTR_X86_MMX_EMMS = 312 -INTR_X86_MMX_FEMMS = 313 -INTR_X86_MMX_MASKMOVQ = 314 -INTR_X86_MMX_MOVNT_DQ = 315 -INTR_X86_MMX_PACKSSDW = 316 -INTR_X86_MMX_PACKSSWB = 317 -INTR_X86_MMX_PACKUSWB = 318 -INTR_X86_MMX_PADDS_B = 319 -INTR_X86_MMX_PADDS_W = 320 -INTR_X86_MMX_PADDUS_B = 321 -INTR_X86_MMX_PADDUS_W = 322 -INTR_X86_MMX_PAVG_B = 323 -INTR_X86_MMX_PAVG_W = 324 -INTR_X86_MMX_PCMPEQ_B = 325 -INTR_X86_MMX_PCMPEQ_D = 326 -INTR_X86_MMX_PCMPEQ_W = 327 -INTR_X86_MMX_PCMPGT_B = 328 -INTR_X86_MMX_PCMPGT_D = 329 -INTR_X86_MMX_PCMPGT_W = 330 -INTR_X86_MMX_PMADD_WD = 331 -INTR_X86_MMX_PMAXS_W = 332 -INTR_X86_MMX_PMAXU_B = 333 -INTR_X86_MMX_PMINS_W = 334 -INTR_X86_MMX_PMINU_B = 335 -INTR_X86_MMX_PMOVMSKB = 336 -INTR_X86_MMX_PMULH_W = 337 -INTR_X86_MMX_PMULHU_W = 338 -INTR_X86_MMX_PMULU_DQ = 339 -INTR_X86_MMX_PSAD_BW = 340 -INTR_X86_MMX_PSLL_D = 341 -INTR_X86_MMX_PSLL_Q = 342 -INTR_X86_MMX_PSLL_W = 343 -INTR_X86_MMX_PSLLI_D = 344 -INTR_X86_MMX_PSLLI_Q = 345 -INTR_X86_MMX_PSLLI_W = 346 -INTR_X86_MMX_PSRA_D = 347 -INTR_X86_MMX_PSRA_W = 348 -INTR_X86_MMX_PSRAI_D = 349 -INTR_X86_MMX_PSRAI_W = 350 -INTR_X86_MMX_PSRL_D = 351 -INTR_X86_MMX_PSRL_Q = 352 -INTR_X86_MMX_PSRL_W = 353 -INTR_X86_MMX_PSRLI_D = 354 -INTR_X86_MMX_PSRLI_Q = 355 -INTR_X86_MMX_PSRLI_W = 356 -INTR_X86_MMX_PSUBS_B = 357 -INTR_X86_MMX_PSUBS_W = 358 -INTR_X86_MMX_PSUBUS_B = 359 -INTR_X86_MMX_PSUBUS_W = 360 -INTR_X86_SSE2_ADD_SD = 361 -INTR_X86_SSE2_CLFLUSH = 362 -INTR_X86_SSE2_CMP_PD = 363 -INTR_X86_SSE2_CMP_SD = 364 -INTR_X86_SSE2_COMIEQ_SD = 365 -INTR_X86_SSE2_COMIGE_SD = 366 -INTR_X86_SSE2_COMIGT_SD = 367 -INTR_X86_SSE2_COMILE_SD = 368 -INTR_X86_SSE2_COMILT_SD = 369 -INTR_X86_SSE2_COMINEQ_SD = 370 -INTR_X86_SSE2_CVTDQ2PD = 371 -INTR_X86_SSE2_CVTDQ2PS = 372 -INTR_X86_SSE2_CVTPD2DQ = 373 -INTR_X86_SSE2_CVTPD2PS = 374 -INTR_X86_SSE2_CVTPS2DQ = 375 -INTR_X86_SSE2_CVTPS2PD = 376 -INTR_X86_SSE2_CVTSD2SI = 377 -INTR_X86_SSE2_CVTSD2SI64 = 378 -INTR_X86_SSE2_CVTSD2SS = 379 -INTR_X86_SSE2_CVTSI2SD = 380 -INTR_X86_SSE2_CVTSI642SD = 381 -INTR_X86_SSE2_CVTSS2SD = 382 -INTR_X86_SSE2_CVTTPD2DQ = 383 -INTR_X86_SSE2_CVTTPS2DQ = 384 -INTR_X86_SSE2_CVTTSD2SI = 385 -INTR_X86_SSE2_CVTTSD2SI64 = 386 -INTR_X86_SSE2_DIV_SD = 387 -INTR_X86_SSE2_LFENCE = 388 -INTR_X86_SSE2_LOADU_DQ = 389 -INTR_X86_SSE2_LOADU_PD = 390 -INTR_X86_SSE2_MASKMOV_DQU = 391 -INTR_X86_SSE2_MAX_PD = 392 -INTR_X86_SSE2_MAX_SD = 393 -INTR_X86_SSE2_MFENCE = 394 -INTR_X86_SSE2_MIN_PD = 395 -INTR_X86_SSE2_MIN_SD = 396 -INTR_X86_SSE2_MOVMSK_PD = 397 -INTR_X86_SSE2_MOVNT_DQ = 398 -INTR_X86_SSE2_MOVNT_I = 399 -INTR_X86_SSE2_MOVNT_PD = 400 -INTR_X86_SSE2_MUL_SD = 401 -INTR_X86_SSE2_PACKSSDW_128 = 402 -INTR_X86_SSE2_PACKSSWB_128 = 403 -INTR_X86_SSE2_PACKUSWB_128 = 404 -INTR_X86_SSE2_PADDS_B = 405 -INTR_X86_SSE2_PADDS_W = 406 -INTR_X86_SSE2_PADDUS_B = 407 -INTR_X86_SSE2_PADDUS_W = 408 -INTR_X86_SSE2_PAVG_B = 409 -INTR_X86_SSE2_PAVG_W = 410 -INTR_X86_SSE2_PCMPEQ_B = 411 -INTR_X86_SSE2_PCMPEQ_D = 412 -INTR_X86_SSE2_PCMPEQ_W = 413 -INTR_X86_SSE2_PCMPGT_B = 414 -INTR_X86_SSE2_PCMPGT_D = 415 -INTR_X86_SSE2_PCMPGT_W = 416 -INTR_X86_SSE2_PMADD_WD = 417 -INTR_X86_SSE2_PMAXS_W = 418 -INTR_X86_SSE2_PMAXU_B = 419 -INTR_X86_SSE2_PMINS_W = 420 -INTR_X86_SSE2_PMINU_B = 421 -INTR_X86_SSE2_PMOVMSKB_128 = 422 -INTR_X86_SSE2_PMULH_W = 423 -INTR_X86_SSE2_PMULHU_W = 424 -INTR_X86_SSE2_PMULU_DQ = 425 -INTR_X86_SSE2_PSAD_BW = 426 -INTR_X86_SSE2_PSLL_D = 427 -INTR_X86_SSE2_PSLL_DQ = 428 -INTR_X86_SSE2_PSLL_DQ_BS = 429 -INTR_X86_SSE2_PSLL_Q = 430 -INTR_X86_SSE2_PSLL_W = 431 -INTR_X86_SSE2_PSLLI_D = 432 -INTR_X86_SSE2_PSLLI_Q = 433 -INTR_X86_SSE2_PSLLI_W = 434 -INTR_X86_SSE2_PSRA_D = 435 -INTR_X86_SSE2_PSRA_W = 436 -INTR_X86_SSE2_PSRAI_D = 437 -INTR_X86_SSE2_PSRAI_W = 438 -INTR_X86_SSE2_PSRL_D = 439 -INTR_X86_SSE2_PSRL_DQ = 440 -INTR_X86_SSE2_PSRL_DQ_BS = 441 -INTR_X86_SSE2_PSRL_Q = 442 -INTR_X86_SSE2_PSRL_W = 443 -INTR_X86_SSE2_PSRLI_D = 444 -INTR_X86_SSE2_PSRLI_Q = 445 -INTR_X86_SSE2_PSRLI_W = 446 -INTR_X86_SSE2_PSUBS_B = 447 -INTR_X86_SSE2_PSUBS_W = 448 -INTR_X86_SSE2_PSUBUS_B = 449 -INTR_X86_SSE2_PSUBUS_W = 450 -INTR_X86_SSE2_SQRT_PD = 451 -INTR_X86_SSE2_SQRT_SD = 452 -INTR_X86_SSE2_STOREL_DQ = 453 -INTR_X86_SSE2_STOREU_DQ = 454 -INTR_X86_SSE2_STOREU_PD = 455 -INTR_X86_SSE2_SUB_SD = 456 -INTR_X86_SSE2_UCOMIEQ_SD = 457 -INTR_X86_SSE2_UCOMIGE_SD = 458 -INTR_X86_SSE2_UCOMIGT_SD = 459 -INTR_X86_SSE2_UCOMILE_SD = 460 -INTR_X86_SSE2_UCOMILT_SD = 461 -INTR_X86_SSE2_UCOMINEQ_SD = 462 -INTR_X86_SSE3_ADDSUB_PD = 463 -INTR_X86_SSE3_ADDSUB_PS = 464 -INTR_X86_SSE3_HADD_PD = 465 -INTR_X86_SSE3_HADD_PS = 466 -INTR_X86_SSE3_HSUB_PD = 467 -INTR_X86_SSE3_HSUB_PS = 468 -INTR_X86_SSE3_LDU_DQ = 469 -INTR_X86_SSE3_MONITOR = 470 -INTR_X86_SSE3_MWAIT = 471 -INTR_X86_SSE41_BLENDPD = 472 -INTR_X86_SSE41_BLENDPS = 473 -INTR_X86_SSE41_BLENDVPD = 474 -INTR_X86_SSE41_BLENDVPS = 475 -INTR_X86_SSE41_DPPD = 476 -INTR_X86_SSE41_DPPS = 477 -INTR_X86_SSE41_EXTRACTPS = 478 -INTR_X86_SSE41_INSERTPS = 479 -INTR_X86_SSE41_MOVNTDQA = 480 -INTR_X86_SSE41_MPSADBW = 481 -INTR_X86_SSE41_PACKUSDW = 482 -INTR_X86_SSE41_PBLENDVB = 483 -INTR_X86_SSE41_PBLENDW = 484 -INTR_X86_SSE41_PCMPEQQ = 485 -INTR_X86_SSE41_PEXTRB = 486 -INTR_X86_SSE41_PEXTRD = 487 -INTR_X86_SSE41_PEXTRQ = 488 -INTR_X86_SSE41_PHMINPOSUW = 489 -INTR_X86_SSE41_PINSRB = 490 -INTR_X86_SSE41_PINSRD = 491 -INTR_X86_SSE41_PINSRQ = 492 -INTR_X86_SSE41_PMAXSB = 493 -INTR_X86_SSE41_PMAXSD = 494 -INTR_X86_SSE41_PMAXUD = 495 -INTR_X86_SSE41_PMAXUW = 496 -INTR_X86_SSE41_PMINSB = 497 -INTR_X86_SSE41_PMINSD = 498 -INTR_X86_SSE41_PMINUD = 499 -INTR_X86_SSE41_PMINUW = 500 -INTR_X86_SSE41_PMOVSXBD = 501 -INTR_X86_SSE41_PMOVSXBQ = 502 -INTR_X86_SSE41_PMOVSXBW = 503 -INTR_X86_SSE41_PMOVSXDQ = 504 -INTR_X86_SSE41_PMOVSXWD = 505 -INTR_X86_SSE41_PMOVSXWQ = 506 -INTR_X86_SSE41_PMOVZXBD = 507 -INTR_X86_SSE41_PMOVZXBQ = 508 -INTR_X86_SSE41_PMOVZXBW = 509 -INTR_X86_SSE41_PMOVZXDQ = 510 -INTR_X86_SSE41_PMOVZXWD = 511 -INTR_X86_SSE41_PMOVZXWQ = 512 -INTR_X86_SSE41_PMULDQ = 513 -INTR_X86_SSE41_PMULLD = 514 -INTR_X86_SSE41_ROUND_PD = 515 -INTR_X86_SSE41_ROUND_PS = 516 -INTR_X86_SSE41_ROUND_SD = 517 -INTR_X86_SSE41_ROUND_SS = 518 -INTR_X86_SSE42_PCMPGTQ = 519 -INTR_X86_SSE_ADD_SS = 520 -INTR_X86_SSE_CMP_PS = 521 -INTR_X86_SSE_CMP_SS = 522 -INTR_X86_SSE_COMIEQ_SS = 523 -INTR_X86_SSE_COMIGE_SS = 524 -INTR_X86_SSE_COMIGT_SS = 525 -INTR_X86_SSE_COMILE_SS = 526 -INTR_X86_SSE_COMILT_SS = 527 -INTR_X86_SSE_COMINEQ_SS = 528 -INTR_X86_SSE_CVTPD2PI = 529 -INTR_X86_SSE_CVTPI2PD = 530 -INTR_X86_SSE_CVTPI2PS = 531 -INTR_X86_SSE_CVTPS2PI = 532 -INTR_X86_SSE_CVTSI2SS = 533 -INTR_X86_SSE_CVTSI642SS = 534 -INTR_X86_SSE_CVTSS2SI = 535 -INTR_X86_SSE_CVTSS2SI64 = 536 -INTR_X86_SSE_CVTTPD2PI = 537 -INTR_X86_SSE_CVTTPS2PI = 538 -INTR_X86_SSE_CVTTSS2SI = 539 -INTR_X86_SSE_CVTTSS2SI64 = 540 -INTR_X86_SSE_DIV_SS = 541 -INTR_X86_SSE_LDMXCSR = 542 -INTR_X86_SSE_LOADU_PS = 543 -INTR_X86_SSE_MAX_PS = 544 -INTR_X86_SSE_MAX_SS = 545 -INTR_X86_SSE_MIN_PS = 546 -INTR_X86_SSE_MIN_SS = 547 -INTR_X86_SSE_MOVMSK_PS = 548 -INTR_X86_SSE_MOVNT_PS = 549 -INTR_X86_SSE_MUL_SS = 550 -INTR_X86_SSE_RCP_PS = 551 -INTR_X86_SSE_RCP_SS = 552 -INTR_X86_SSE_RSQRT_PS = 553 -INTR_X86_SSE_RSQRT_SS = 554 -INTR_X86_SSE_SFENCE = 555 -INTR_X86_SSE_SQRT_PS = 556 -INTR_X86_SSE_SQRT_SS = 557 -INTR_X86_SSE_STMXCSR = 558 -INTR_X86_SSE_STOREU_PS = 559 -INTR_X86_SSE_SUB_SS = 560 -INTR_X86_SSE_UCOMIEQ_SS = 561 -INTR_X86_SSE_UCOMIGE_SS = 562 -INTR_X86_SSE_UCOMIGT_SS = 563 -INTR_X86_SSE_UCOMILE_SS = 564 -INTR_X86_SSE_UCOMILT_SS = 565 -INTR_X86_SSE_UCOMINEQ_SS = 566 -INTR_X86_SSSE3_PABS_B = 567 -INTR_X86_SSSE3_PABS_B_128 = 568 -INTR_X86_SSSE3_PABS_D = 569 -INTR_X86_SSSE3_PABS_D_128 = 570 -INTR_X86_SSSE3_PABS_W = 571 -INTR_X86_SSSE3_PABS_W_128 = 572 -INTR_X86_SSSE3_PALIGN_R = 573 -INTR_X86_SSSE3_PALIGN_R_128 = 574 -INTR_X86_SSSE3_PHADD_D = 575 -INTR_X86_SSSE3_PHADD_D_128 = 576 -INTR_X86_SSSE3_PHADD_SW = 577 -INTR_X86_SSSE3_PHADD_SW_128 = 578 -INTR_X86_SSSE3_PHADD_W = 579 -INTR_X86_SSSE3_PHADD_W_128 = 580 -INTR_X86_SSSE3_PHSUB_D = 581 -INTR_X86_SSSE3_PHSUB_D_128 = 582 -INTR_X86_SSSE3_PHSUB_SW = 583 -INTR_X86_SSSE3_PHSUB_SW_128 = 584 -INTR_X86_SSSE3_PHSUB_W = 585 -INTR_X86_SSSE3_PHSUB_W_128 = 586 -INTR_X86_SSSE3_PMADD_UB_SW = 587 -INTR_X86_SSSE3_PMADD_UB_SW_128 = 588 -INTR_X86_SSSE3_PMUL_HR_SW = 589 -INTR_X86_SSSE3_PMUL_HR_SW_128 = 590 -INTR_X86_SSSE3_PSHUF_B = 591 -INTR_X86_SSSE3_PSHUF_B_128 = 592 -INTR_X86_SSSE3_PSIGN_B = 593 -INTR_X86_SSSE3_PSIGN_B_128 = 594 -INTR_X86_SSSE3_PSIGN_D = 595 -INTR_X86_SSSE3_PSIGN_D_128 = 596 -INTR_X86_SSSE3_PSIGN_W = 597 -INTR_X86_SSSE3_PSIGN_W_128 = 598 +INTR_CONVERTFF = 17 +INTR_CONVERTFSI = 18 +INTR_CONVERTFUI = 19 +INTR_CONVERTSIF = 20 +INTR_CONVERTSS = 21 +INTR_CONVERTSU = 22 +INTR_CONVERTUIF = 23 +INTR_CONVERTUS = 24 +INTR_CONVERTUU = 25 +INTR_COS = 26 +INTR_CTLZ = 27 +INTR_CTPOP = 28 +INTR_CTTZ = 29 +INTR_DBG_DECLARE = 30 +INTR_DBG_FUNC_START = 31 +INTR_DBG_REGION_END = 32 +INTR_DBG_REGION_START = 33 +INTR_DBG_STOPPOINT = 34 +INTR_EH_DWARF_CFA = 35 +INTR_EH_EXCEPTION = 36 +INTR_EH_RETURN_I32 = 37 +INTR_EH_RETURN_I64 = 38 +INTR_EH_SELECTOR_I32 = 39 +INTR_EH_SELECTOR_I64 = 40 +INTR_EH_TYPEID_FOR_I32 = 41 +INTR_EH_TYPEID_FOR_I64 = 42 +INTR_EH_UNWIND_INIT = 43 +INTR_EXP = 44 +INTR_EXP2 = 45 +INTR_FLT_ROUNDS = 46 +INTR_FRAMEADDRESS = 47 +INTR_GCREAD = 48 +INTR_GCROOT = 49 +INTR_GCWRITE = 50 +INTR_INIT_TRAMPOLINE = 51 +INTR_LOG = 52 +INTR_LOG10 = 53 +INTR_LOG2 = 54 +INTR_LONGJMP = 55 +INTR_MEMCPY = 56 +INTR_MEMMOVE = 57 +INTR_MEMORY_BARRIER = 58 +INTR_MEMSET = 59 +INTR_PART_SELECT = 60 +INTR_PART_SET = 61 +INTR_PCMARKER = 62 +INTR_POW = 63 +INTR_POWI = 64 +INTR_PPC_ALTIVEC_DSS = 65 +INTR_PPC_ALTIVEC_DSSALL = 66 +INTR_PPC_ALTIVEC_DST = 67 +INTR_PPC_ALTIVEC_DSTST = 68 +INTR_PPC_ALTIVEC_DSTSTT = 69 +INTR_PPC_ALTIVEC_DSTT = 70 +INTR_PPC_ALTIVEC_LVEBX = 71 +INTR_PPC_ALTIVEC_LVEHX = 72 +INTR_PPC_ALTIVEC_LVEWX = 73 +INTR_PPC_ALTIVEC_LVSL = 74 +INTR_PPC_ALTIVEC_LVSR = 75 +INTR_PPC_ALTIVEC_LVX = 76 +INTR_PPC_ALTIVEC_LVXL = 77 +INTR_PPC_ALTIVEC_MFVSCR = 78 +INTR_PPC_ALTIVEC_MTVSCR = 79 +INTR_PPC_ALTIVEC_STVEBX = 80 +INTR_PPC_ALTIVEC_STVEHX = 81 +INTR_PPC_ALTIVEC_STVEWX = 82 +INTR_PPC_ALTIVEC_STVX = 83 +INTR_PPC_ALTIVEC_STVXL = 84 +INTR_PPC_ALTIVEC_VADDCUW = 85 +INTR_PPC_ALTIVEC_VADDSBS = 86 +INTR_PPC_ALTIVEC_VADDSHS = 87 +INTR_PPC_ALTIVEC_VADDSWS = 88 +INTR_PPC_ALTIVEC_VADDUBS = 89 +INTR_PPC_ALTIVEC_VADDUHS = 90 +INTR_PPC_ALTIVEC_VADDUWS = 91 +INTR_PPC_ALTIVEC_VAVGSB = 92 +INTR_PPC_ALTIVEC_VAVGSH = 93 +INTR_PPC_ALTIVEC_VAVGSW = 94 +INTR_PPC_ALTIVEC_VAVGUB = 95 +INTR_PPC_ALTIVEC_VAVGUH = 96 +INTR_PPC_ALTIVEC_VAVGUW = 97 +INTR_PPC_ALTIVEC_VCFSX = 98 +INTR_PPC_ALTIVEC_VCFUX = 99 +INTR_PPC_ALTIVEC_VCMPBFP = 100 +INTR_PPC_ALTIVEC_VCMPBFP_P = 101 +INTR_PPC_ALTIVEC_VCMPEQFP = 102 +INTR_PPC_ALTIVEC_VCMPEQFP_P = 103 +INTR_PPC_ALTIVEC_VCMPEQUB = 104 +INTR_PPC_ALTIVEC_VCMPEQUB_P = 105 +INTR_PPC_ALTIVEC_VCMPEQUH = 106 +INTR_PPC_ALTIVEC_VCMPEQUH_P = 107 +INTR_PPC_ALTIVEC_VCMPEQUW = 108 +INTR_PPC_ALTIVEC_VCMPEQUW_P = 109 +INTR_PPC_ALTIVEC_VCMPGEFP = 110 +INTR_PPC_ALTIVEC_VCMPGEFP_P = 111 +INTR_PPC_ALTIVEC_VCMPGTFP = 112 +INTR_PPC_ALTIVEC_VCMPGTFP_P = 113 +INTR_PPC_ALTIVEC_VCMPGTSB = 114 +INTR_PPC_ALTIVEC_VCMPGTSB_P = 115 +INTR_PPC_ALTIVEC_VCMPGTSH = 116 +INTR_PPC_ALTIVEC_VCMPGTSH_P = 117 +INTR_PPC_ALTIVEC_VCMPGTSW = 118 +INTR_PPC_ALTIVEC_VCMPGTSW_P = 119 +INTR_PPC_ALTIVEC_VCMPGTUB = 120 +INTR_PPC_ALTIVEC_VCMPGTUB_P = 121 +INTR_PPC_ALTIVEC_VCMPGTUH = 122 +INTR_PPC_ALTIVEC_VCMPGTUH_P = 123 +INTR_PPC_ALTIVEC_VCMPGTUW = 124 +INTR_PPC_ALTIVEC_VCMPGTUW_P = 125 +INTR_PPC_ALTIVEC_VCTSXS = 126 +INTR_PPC_ALTIVEC_VCTUXS = 127 +INTR_PPC_ALTIVEC_VEXPTEFP = 128 +INTR_PPC_ALTIVEC_VLOGEFP = 129 +INTR_PPC_ALTIVEC_VMADDFP = 130 +INTR_PPC_ALTIVEC_VMAXFP = 131 +INTR_PPC_ALTIVEC_VMAXSB = 132 +INTR_PPC_ALTIVEC_VMAXSH = 133 +INTR_PPC_ALTIVEC_VMAXSW = 134 +INTR_PPC_ALTIVEC_VMAXUB = 135 +INTR_PPC_ALTIVEC_VMAXUH = 136 +INTR_PPC_ALTIVEC_VMAXUW = 137 +INTR_PPC_ALTIVEC_VMHADDSHS = 138 +INTR_PPC_ALTIVEC_VMHRADDSHS = 139 +INTR_PPC_ALTIVEC_VMINFP = 140 +INTR_PPC_ALTIVEC_VMINSB = 141 +INTR_PPC_ALTIVEC_VMINSH = 142 +INTR_PPC_ALTIVEC_VMINSW = 143 +INTR_PPC_ALTIVEC_VMINUB = 144 +INTR_PPC_ALTIVEC_VMINUH = 145 +INTR_PPC_ALTIVEC_VMINUW = 146 +INTR_PPC_ALTIVEC_VMLADDUHM = 147 +INTR_PPC_ALTIVEC_VMSUMMBM = 148 +INTR_PPC_ALTIVEC_VMSUMSHM = 149 +INTR_PPC_ALTIVEC_VMSUMSHS = 150 +INTR_PPC_ALTIVEC_VMSUMUBM = 151 +INTR_PPC_ALTIVEC_VMSUMUHM = 152 +INTR_PPC_ALTIVEC_VMSUMUHS = 153 +INTR_PPC_ALTIVEC_VMULESB = 154 +INTR_PPC_ALTIVEC_VMULESH = 155 +INTR_PPC_ALTIVEC_VMULEUB = 156 +INTR_PPC_ALTIVEC_VMULEUH = 157 +INTR_PPC_ALTIVEC_VMULOSB = 158 +INTR_PPC_ALTIVEC_VMULOSH = 159 +INTR_PPC_ALTIVEC_VMULOUB = 160 +INTR_PPC_ALTIVEC_VMULOUH = 161 +INTR_PPC_ALTIVEC_VNMSUBFP = 162 +INTR_PPC_ALTIVEC_VPERM = 163 +INTR_PPC_ALTIVEC_VPKPX = 164 +INTR_PPC_ALTIVEC_VPKSHSS = 165 +INTR_PPC_ALTIVEC_VPKSHUS = 166 +INTR_PPC_ALTIVEC_VPKSWSS = 167 +INTR_PPC_ALTIVEC_VPKSWUS = 168 +INTR_PPC_ALTIVEC_VPKUHUS = 169 +INTR_PPC_ALTIVEC_VPKUWUS = 170 +INTR_PPC_ALTIVEC_VREFP = 171 +INTR_PPC_ALTIVEC_VRFIM = 172 +INTR_PPC_ALTIVEC_VRFIN = 173 +INTR_PPC_ALTIVEC_VRFIP = 174 +INTR_PPC_ALTIVEC_VRFIZ = 175 +INTR_PPC_ALTIVEC_VRLB = 176 +INTR_PPC_ALTIVEC_VRLH = 177 +INTR_PPC_ALTIVEC_VRLW = 178 +INTR_PPC_ALTIVEC_VRSQRTEFP = 179 +INTR_PPC_ALTIVEC_VSEL = 180 +INTR_PPC_ALTIVEC_VSL = 181 +INTR_PPC_ALTIVEC_VSLB = 182 +INTR_PPC_ALTIVEC_VSLH = 183 +INTR_PPC_ALTIVEC_VSLO = 184 +INTR_PPC_ALTIVEC_VSLW = 185 +INTR_PPC_ALTIVEC_VSR = 186 +INTR_PPC_ALTIVEC_VSRAB = 187 +INTR_PPC_ALTIVEC_VSRAH = 188 +INTR_PPC_ALTIVEC_VSRAW = 189 +INTR_PPC_ALTIVEC_VSRB = 190 +INTR_PPC_ALTIVEC_VSRH = 191 +INTR_PPC_ALTIVEC_VSRO = 192 +INTR_PPC_ALTIVEC_VSRW = 193 +INTR_PPC_ALTIVEC_VSUBCUW = 194 +INTR_PPC_ALTIVEC_VSUBSBS = 195 +INTR_PPC_ALTIVEC_VSUBSHS = 196 +INTR_PPC_ALTIVEC_VSUBSWS = 197 +INTR_PPC_ALTIVEC_VSUBUBS = 198 +INTR_PPC_ALTIVEC_VSUBUHS = 199 +INTR_PPC_ALTIVEC_VSUBUWS = 200 +INTR_PPC_ALTIVEC_VSUM2SWS = 201 +INTR_PPC_ALTIVEC_VSUM4SBS = 202 +INTR_PPC_ALTIVEC_VSUM4SHS = 203 +INTR_PPC_ALTIVEC_VSUM4UBS = 204 +INTR_PPC_ALTIVEC_VSUMSWS = 205 +INTR_PPC_ALTIVEC_VUPKHPX = 206 +INTR_PPC_ALTIVEC_VUPKHSB = 207 +INTR_PPC_ALTIVEC_VUPKHSH = 208 +INTR_PPC_ALTIVEC_VUPKLPX = 209 +INTR_PPC_ALTIVEC_VUPKLSB = 210 +INTR_PPC_ALTIVEC_VUPKLSH = 211 +INTR_PPC_DCBA = 212 +INTR_PPC_DCBF = 213 +INTR_PPC_DCBI = 214 +INTR_PPC_DCBST = 215 +INTR_PPC_DCBT = 216 +INTR_PPC_DCBTST = 217 +INTR_PPC_DCBZ = 218 +INTR_PPC_DCBZL = 219 +INTR_PPC_SYNC = 220 +INTR_PREFETCH = 221 +INTR_PTR_ANNOTATION = 222 +INTR_READCYCLECOUNTER = 223 +INTR_RETURNADDRESS = 224 +INTR_SADD_WITH_OVERFLOW = 225 +INTR_SETJMP = 226 +INTR_SIGLONGJMP = 227 +INTR_SIGSETJMP = 228 +INTR_SIN = 229 +INTR_SMUL_WITH_OVERFLOW = 230 +INTR_SPU_SI_A = 231 +INTR_SPU_SI_ADDX = 232 +INTR_SPU_SI_AH = 233 +INTR_SPU_SI_AHI = 234 +INTR_SPU_SI_AI = 235 +INTR_SPU_SI_AND = 236 +INTR_SPU_SI_ANDBI = 237 +INTR_SPU_SI_ANDC = 238 +INTR_SPU_SI_ANDHI = 239 +INTR_SPU_SI_ANDI = 240 +INTR_SPU_SI_BG = 241 +INTR_SPU_SI_BGX = 242 +INTR_SPU_SI_CEQ = 243 +INTR_SPU_SI_CEQB = 244 +INTR_SPU_SI_CEQBI = 245 +INTR_SPU_SI_CEQH = 246 +INTR_SPU_SI_CEQHI = 247 +INTR_SPU_SI_CEQI = 248 +INTR_SPU_SI_CG = 249 +INTR_SPU_SI_CGT = 250 +INTR_SPU_SI_CGTB = 251 +INTR_SPU_SI_CGTBI = 252 +INTR_SPU_SI_CGTH = 253 +INTR_SPU_SI_CGTHI = 254 +INTR_SPU_SI_CGTI = 255 +INTR_SPU_SI_CGX = 256 +INTR_SPU_SI_CLGT = 257 +INTR_SPU_SI_CLGTB = 258 +INTR_SPU_SI_CLGTBI = 259 +INTR_SPU_SI_CLGTH = 260 +INTR_SPU_SI_CLGTHI = 261 +INTR_SPU_SI_CLGTI = 262 +INTR_SPU_SI_DFA = 263 +INTR_SPU_SI_DFM = 264 +INTR_SPU_SI_DFMA = 265 +INTR_SPU_SI_DFMS = 266 +INTR_SPU_SI_DFNMA = 267 +INTR_SPU_SI_DFNMS = 268 +INTR_SPU_SI_DFS = 269 +INTR_SPU_SI_FA = 270 +INTR_SPU_SI_FCEQ = 271 +INTR_SPU_SI_FCGT = 272 +INTR_SPU_SI_FCMEQ = 273 +INTR_SPU_SI_FCMGT = 274 +INTR_SPU_SI_FM = 275 +INTR_SPU_SI_FMA = 276 +INTR_SPU_SI_FMS = 277 +INTR_SPU_SI_FNMS = 278 +INTR_SPU_SI_FS = 279 +INTR_SPU_SI_FSMBI = 280 +INTR_SPU_SI_MPY = 281 +INTR_SPU_SI_MPYA = 282 +INTR_SPU_SI_MPYH = 283 +INTR_SPU_SI_MPYHH = 284 +INTR_SPU_SI_MPYHHA = 285 +INTR_SPU_SI_MPYHHAU = 286 +INTR_SPU_SI_MPYHHU = 287 +INTR_SPU_SI_MPYI = 288 +INTR_SPU_SI_MPYS = 289 +INTR_SPU_SI_MPYU = 290 +INTR_SPU_SI_MPYUI = 291 +INTR_SPU_SI_NAND = 292 +INTR_SPU_SI_NOR = 293 +INTR_SPU_SI_OR = 294 +INTR_SPU_SI_ORBI = 295 +INTR_SPU_SI_ORC = 296 +INTR_SPU_SI_ORHI = 297 +INTR_SPU_SI_ORI = 298 +INTR_SPU_SI_SF = 299 +INTR_SPU_SI_SFH = 300 +INTR_SPU_SI_SFHI = 301 +INTR_SPU_SI_SFI = 302 +INTR_SPU_SI_SFX = 303 +INTR_SPU_SI_SHLI = 304 +INTR_SPU_SI_SHLQBI = 305 +INTR_SPU_SI_SHLQBII = 306 +INTR_SPU_SI_SHLQBY = 307 +INTR_SPU_SI_SHLQBYI = 308 +INTR_SPU_SI_XOR = 309 +INTR_SPU_SI_XORBI = 310 +INTR_SPU_SI_XORHI = 311 +INTR_SPU_SI_XORI = 312 +INTR_SQRT = 313 +INTR_SSUB_WITH_OVERFLOW = 314 +INTR_STACKPROTECTOR = 315 +INTR_STACKRESTORE = 316 +INTR_STACKSAVE = 317 +INTR_TRAP = 318 +INTR_UADD_WITH_OVERFLOW = 319 +INTR_UMUL_WITH_OVERFLOW = 320 +INTR_USUB_WITH_OVERFLOW = 321 +INTR_VACOPY = 322 +INTR_VAEND = 323 +INTR_VAR_ANNOTATION = 324 +INTR_VASTART = 325 +INTR_X86_MMX_EMMS = 326 +INTR_X86_MMX_FEMMS = 327 +INTR_X86_MMX_MASKMOVQ = 328 +INTR_X86_MMX_MOVNT_DQ = 329 +INTR_X86_MMX_PACKSSDW = 330 +INTR_X86_MMX_PACKSSWB = 331 +INTR_X86_MMX_PACKUSWB = 332 +INTR_X86_MMX_PADDS_B = 333 +INTR_X86_MMX_PADDS_W = 334 +INTR_X86_MMX_PADDUS_B = 335 +INTR_X86_MMX_PADDUS_W = 336 +INTR_X86_MMX_PAVG_B = 337 +INTR_X86_MMX_PAVG_W = 338 +INTR_X86_MMX_PCMPEQ_B = 339 +INTR_X86_MMX_PCMPEQ_D = 340 +INTR_X86_MMX_PCMPEQ_W = 341 +INTR_X86_MMX_PCMPGT_B = 342 +INTR_X86_MMX_PCMPGT_D = 343 +INTR_X86_MMX_PCMPGT_W = 344 +INTR_X86_MMX_PMADD_WD = 345 +INTR_X86_MMX_PMAXS_W = 346 +INTR_X86_MMX_PMAXU_B = 347 +INTR_X86_MMX_PMINS_W = 348 +INTR_X86_MMX_PMINU_B = 349 +INTR_X86_MMX_PMOVMSKB = 350 +INTR_X86_MMX_PMULH_W = 351 +INTR_X86_MMX_PMULHU_W = 352 +INTR_X86_MMX_PMULU_DQ = 353 +INTR_X86_MMX_PSAD_BW = 354 +INTR_X86_MMX_PSLL_D = 355 +INTR_X86_MMX_PSLL_Q = 356 +INTR_X86_MMX_PSLL_W = 357 +INTR_X86_MMX_PSLLI_D = 358 +INTR_X86_MMX_PSLLI_Q = 359 +INTR_X86_MMX_PSLLI_W = 360 +INTR_X86_MMX_PSRA_D = 361 +INTR_X86_MMX_PSRA_W = 362 +INTR_X86_MMX_PSRAI_D = 363 +INTR_X86_MMX_PSRAI_W = 364 +INTR_X86_MMX_PSRL_D = 365 +INTR_X86_MMX_PSRL_Q = 366 +INTR_X86_MMX_PSRL_W = 367 +INTR_X86_MMX_PSRLI_D = 368 +INTR_X86_MMX_PSRLI_Q = 369 +INTR_X86_MMX_PSRLI_W = 370 +INTR_X86_MMX_PSUBS_B = 371 +INTR_X86_MMX_PSUBS_W = 372 +INTR_X86_MMX_PSUBUS_B = 373 +INTR_X86_MMX_PSUBUS_W = 374 +INTR_X86_SSE2_ADD_SD = 375 +INTR_X86_SSE2_CLFLUSH = 376 +INTR_X86_SSE2_CMP_PD = 377 +INTR_X86_SSE2_CMP_SD = 378 +INTR_X86_SSE2_COMIEQ_SD = 379 +INTR_X86_SSE2_COMIGE_SD = 380 +INTR_X86_SSE2_COMIGT_SD = 381 +INTR_X86_SSE2_COMILE_SD = 382 +INTR_X86_SSE2_COMILT_SD = 383 +INTR_X86_SSE2_COMINEQ_SD = 384 +INTR_X86_SSE2_CVTDQ2PD = 385 +INTR_X86_SSE2_CVTDQ2PS = 386 +INTR_X86_SSE2_CVTPD2DQ = 387 +INTR_X86_SSE2_CVTPD2PS = 388 +INTR_X86_SSE2_CVTPS2DQ = 389 +INTR_X86_SSE2_CVTPS2PD = 390 +INTR_X86_SSE2_CVTSD2SI = 391 +INTR_X86_SSE2_CVTSD2SI64 = 392 +INTR_X86_SSE2_CVTSD2SS = 393 +INTR_X86_SSE2_CVTSI2SD = 394 +INTR_X86_SSE2_CVTSI642SD = 395 +INTR_X86_SSE2_CVTSS2SD = 396 +INTR_X86_SSE2_CVTTPD2DQ = 397 +INTR_X86_SSE2_CVTTPS2DQ = 398 +INTR_X86_SSE2_CVTTSD2SI = 399 +INTR_X86_SSE2_CVTTSD2SI64 = 400 +INTR_X86_SSE2_DIV_SD = 401 +INTR_X86_SSE2_LFENCE = 402 +INTR_X86_SSE2_LOADU_DQ = 403 +INTR_X86_SSE2_LOADU_PD = 404 +INTR_X86_SSE2_MASKMOV_DQU = 405 +INTR_X86_SSE2_MAX_PD = 406 +INTR_X86_SSE2_MAX_SD = 407 +INTR_X86_SSE2_MFENCE = 408 +INTR_X86_SSE2_MIN_PD = 409 +INTR_X86_SSE2_MIN_SD = 410 +INTR_X86_SSE2_MOVMSK_PD = 411 +INTR_X86_SSE2_MOVNT_DQ = 412 +INTR_X86_SSE2_MOVNT_I = 413 +INTR_X86_SSE2_MOVNT_PD = 414 +INTR_X86_SSE2_MUL_SD = 415 +INTR_X86_SSE2_PACKSSDW_128 = 416 +INTR_X86_SSE2_PACKSSWB_128 = 417 +INTR_X86_SSE2_PACKUSWB_128 = 418 +INTR_X86_SSE2_PADDS_B = 419 +INTR_X86_SSE2_PADDS_W = 420 +INTR_X86_SSE2_PADDUS_B = 421 +INTR_X86_SSE2_PADDUS_W = 422 +INTR_X86_SSE2_PAVG_B = 423 +INTR_X86_SSE2_PAVG_W = 424 +INTR_X86_SSE2_PCMPEQ_B = 425 +INTR_X86_SSE2_PCMPEQ_D = 426 +INTR_X86_SSE2_PCMPEQ_W = 427 +INTR_X86_SSE2_PCMPGT_B = 428 +INTR_X86_SSE2_PCMPGT_D = 429 +INTR_X86_SSE2_PCMPGT_W = 430 +INTR_X86_SSE2_PMADD_WD = 431 +INTR_X86_SSE2_PMAXS_W = 432 +INTR_X86_SSE2_PMAXU_B = 433 +INTR_X86_SSE2_PMINS_W = 434 +INTR_X86_SSE2_PMINU_B = 435 +INTR_X86_SSE2_PMOVMSKB_128 = 436 +INTR_X86_SSE2_PMULH_W = 437 +INTR_X86_SSE2_PMULHU_W = 438 +INTR_X86_SSE2_PMULU_DQ = 439 +INTR_X86_SSE2_PSAD_BW = 440 +INTR_X86_SSE2_PSLL_D = 441 +INTR_X86_SSE2_PSLL_DQ = 442 +INTR_X86_SSE2_PSLL_DQ_BS = 443 +INTR_X86_SSE2_PSLL_Q = 444 +INTR_X86_SSE2_PSLL_W = 445 +INTR_X86_SSE2_PSLLI_D = 446 +INTR_X86_SSE2_PSLLI_Q = 447 +INTR_X86_SSE2_PSLLI_W = 448 +INTR_X86_SSE2_PSRA_D = 449 +INTR_X86_SSE2_PSRA_W = 450 +INTR_X86_SSE2_PSRAI_D = 451 +INTR_X86_SSE2_PSRAI_W = 452 +INTR_X86_SSE2_PSRL_D = 453 +INTR_X86_SSE2_PSRL_DQ = 454 +INTR_X86_SSE2_PSRL_DQ_BS = 455 +INTR_X86_SSE2_PSRL_Q = 456 +INTR_X86_SSE2_PSRL_W = 457 +INTR_X86_SSE2_PSRLI_D = 458 +INTR_X86_SSE2_PSRLI_Q = 459 +INTR_X86_SSE2_PSRLI_W = 460 +INTR_X86_SSE2_PSUBS_B = 461 +INTR_X86_SSE2_PSUBS_W = 462 +INTR_X86_SSE2_PSUBUS_B = 463 +INTR_X86_SSE2_PSUBUS_W = 464 +INTR_X86_SSE2_SQRT_PD = 465 +INTR_X86_SSE2_SQRT_SD = 466 +INTR_X86_SSE2_STOREL_DQ = 467 +INTR_X86_SSE2_STOREU_DQ = 468 +INTR_X86_SSE2_STOREU_PD = 469 +INTR_X86_SSE2_SUB_SD = 470 +INTR_X86_SSE2_UCOMIEQ_SD = 471 +INTR_X86_SSE2_UCOMIGE_SD = 472 +INTR_X86_SSE2_UCOMIGT_SD = 473 +INTR_X86_SSE2_UCOMILE_SD = 474 +INTR_X86_SSE2_UCOMILT_SD = 475 +INTR_X86_SSE2_UCOMINEQ_SD = 476 +INTR_X86_SSE3_ADDSUB_PD = 477 +INTR_X86_SSE3_ADDSUB_PS = 478 +INTR_X86_SSE3_HADD_PD = 479 +INTR_X86_SSE3_HADD_PS = 480 +INTR_X86_SSE3_HSUB_PD = 481 +INTR_X86_SSE3_HSUB_PS = 482 +INTR_X86_SSE3_LDU_DQ = 483 +INTR_X86_SSE3_MONITOR = 484 +INTR_X86_SSE3_MWAIT = 485 +INTR_X86_SSE41_BLENDPD = 486 +INTR_X86_SSE41_BLENDPS = 487 +INTR_X86_SSE41_BLENDVPD = 488 +INTR_X86_SSE41_BLENDVPS = 489 +INTR_X86_SSE41_DPPD = 490 +INTR_X86_SSE41_DPPS = 491 +INTR_X86_SSE41_EXTRACTPS = 492 +INTR_X86_SSE41_INSERTPS = 493 +INTR_X86_SSE41_MOVNTDQA = 494 +INTR_X86_SSE41_MPSADBW = 495 +INTR_X86_SSE41_PACKUSDW = 496 +INTR_X86_SSE41_PBLENDVB = 497 +INTR_X86_SSE41_PBLENDW = 498 +INTR_X86_SSE41_PCMPEQQ = 499 +INTR_X86_SSE41_PEXTRB = 500 +INTR_X86_SSE41_PEXTRD = 501 +INTR_X86_SSE41_PEXTRQ = 502 +INTR_X86_SSE41_PHMINPOSUW = 503 +INTR_X86_SSE41_PINSRB = 504 +INTR_X86_SSE41_PMAXSB = 505 +INTR_X86_SSE41_PMAXSD = 506 +INTR_X86_SSE41_PMAXUD = 507 +INTR_X86_SSE41_PMAXUW = 508 +INTR_X86_SSE41_PMINSB = 509 +INTR_X86_SSE41_PMINSD = 510 +INTR_X86_SSE41_PMINUD = 511 +INTR_X86_SSE41_PMINUW = 512 +INTR_X86_SSE41_PMOVSXBD = 513 +INTR_X86_SSE41_PMOVSXBQ = 514 +INTR_X86_SSE41_PMOVSXBW = 515 +INTR_X86_SSE41_PMOVSXDQ = 516 +INTR_X86_SSE41_PMOVSXWD = 517 +INTR_X86_SSE41_PMOVSXWQ = 518 +INTR_X86_SSE41_PMOVZXBD = 519 +INTR_X86_SSE41_PMOVZXBQ = 520 +INTR_X86_SSE41_PMOVZXBW = 521 +INTR_X86_SSE41_PMOVZXDQ = 522 +INTR_X86_SSE41_PMOVZXWD = 523 +INTR_X86_SSE41_PMOVZXWQ = 524 +INTR_X86_SSE41_PMULDQ = 525 +INTR_X86_SSE41_PMULLD = 526 +INTR_X86_SSE41_ROUND_PD = 527 +INTR_X86_SSE41_ROUND_PS = 528 +INTR_X86_SSE41_ROUND_SD = 529 +INTR_X86_SSE41_ROUND_SS = 530 +INTR_X86_SSE42_PCMPGTQ = 531 +INTR_X86_SSE_ADD_SS = 532 +INTR_X86_SSE_CMP_PS = 533 +INTR_X86_SSE_CMP_SS = 534 +INTR_X86_SSE_COMIEQ_SS = 535 +INTR_X86_SSE_COMIGE_SS = 536 +INTR_X86_SSE_COMIGT_SS = 537 +INTR_X86_SSE_COMILE_SS = 538 +INTR_X86_SSE_COMILT_SS = 539 +INTR_X86_SSE_COMINEQ_SS = 540 +INTR_X86_SSE_CVTPD2PI = 541 +INTR_X86_SSE_CVTPI2PD = 542 +INTR_X86_SSE_CVTPI2PS = 543 +INTR_X86_SSE_CVTPS2PI = 544 +INTR_X86_SSE_CVTSI2SS = 545 +INTR_X86_SSE_CVTSI642SS = 546 +INTR_X86_SSE_CVTSS2SI = 547 +INTR_X86_SSE_CVTSS2SI64 = 548 +INTR_X86_SSE_CVTTPD2PI = 549 +INTR_X86_SSE_CVTTPS2PI = 550 +INTR_X86_SSE_CVTTSS2SI = 551 +INTR_X86_SSE_CVTTSS2SI64 = 552 +INTR_X86_SSE_DIV_SS = 553 +INTR_X86_SSE_LDMXCSR = 554 +INTR_X86_SSE_LOADU_PS = 555 +INTR_X86_SSE_MAX_PS = 556 +INTR_X86_SSE_MAX_SS = 557 +INTR_X86_SSE_MIN_PS = 558 +INTR_X86_SSE_MIN_SS = 559 +INTR_X86_SSE_MOVMSK_PS = 560 +INTR_X86_SSE_MOVNT_PS = 561 +INTR_X86_SSE_MUL_SS = 562 +INTR_X86_SSE_RCP_PS = 563 +INTR_X86_SSE_RCP_SS = 564 +INTR_X86_SSE_RSQRT_PS = 565 +INTR_X86_SSE_RSQRT_SS = 566 +INTR_X86_SSE_SFENCE = 567 +INTR_X86_SSE_SQRT_PS = 568 +INTR_X86_SSE_SQRT_SS = 569 +INTR_X86_SSE_STMXCSR = 570 +INTR_X86_SSE_STOREU_PS = 571 +INTR_X86_SSE_SUB_SS = 572 +INTR_X86_SSE_UCOMIEQ_SS = 573 +INTR_X86_SSE_UCOMIGE_SS = 574 +INTR_X86_SSE_UCOMIGT_SS = 575 +INTR_X86_SSE_UCOMILE_SS = 576 +INTR_X86_SSE_UCOMILT_SS = 577 +INTR_X86_SSE_UCOMINEQ_SS = 578 +INTR_X86_SSSE3_PABS_B = 579 +INTR_X86_SSSE3_PABS_B_128 = 580 +INTR_X86_SSSE3_PABS_D = 581 +INTR_X86_SSSE3_PABS_D_128 = 582 +INTR_X86_SSSE3_PABS_W = 583 +INTR_X86_SSSE3_PABS_W_128 = 584 +INTR_X86_SSSE3_PALIGN_R = 585 +INTR_X86_SSSE3_PALIGN_R_128 = 586 +INTR_X86_SSSE3_PHADD_D = 587 +INTR_X86_SSSE3_PHADD_D_128 = 588 +INTR_X86_SSSE3_PHADD_SW = 589 +INTR_X86_SSSE3_PHADD_SW_128 = 590 +INTR_X86_SSSE3_PHADD_W = 591 +INTR_X86_SSSE3_PHADD_W_128 = 592 +INTR_X86_SSSE3_PHSUB_D = 593 +INTR_X86_SSSE3_PHSUB_D_128 = 594 +INTR_X86_SSSE3_PHSUB_SW = 595 +INTR_X86_SSSE3_PHSUB_SW_128 = 596 +INTR_X86_SSSE3_PHSUB_W = 597 +INTR_X86_SSSE3_PHSUB_W_128 = 598 +INTR_X86_SSSE3_PMADD_UB_SW = 599 +INTR_X86_SSSE3_PMADD_UB_SW_128 = 600 +INTR_X86_SSSE3_PMUL_HR_SW = 601 +INTR_X86_SSSE3_PMUL_HR_SW_128 = 602 +INTR_X86_SSSE3_PSHUF_B = 603 +INTR_X86_SSSE3_PSHUF_B_128 = 604 +INTR_X86_SSSE3_PSIGN_B = 605 +INTR_X86_SSSE3_PSIGN_B_128 = 606 +INTR_X86_SSSE3_PSIGN_D = 607 +INTR_X86_SSSE3_PSIGN_D_128 = 608 +INTR_X86_SSSE3_PSIGN_W = 609 +INTR_X86_SSSE3_PSIGN_W_128 = 610 +INTR_XCORE_BITREV = 611 +INTR_XCORE_GETID = 612 #===----------------------------------------------------------------------=== diff --git a/tools/intrgen.py b/tools/intrgen.py new file mode 100755 index 0000000..26e0f8b --- /dev/null +++ b/tools/intrgen.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python +# +# Script to generate intrinsic IDs (found in core.py) from +# /include/llvm/Intrinsics.gen. Call with path to the +# latter. + +import sys + +def gen(f): + intr = [] + maxw = 0 + flag = False + for line in open(f): + if line.startswith('#ifdef GET_INTRINSIC_ENUM_VALUES'): + flag = True + elif flag: + if line.startswith('#endif'): + break + else: + item = line.split()[0].replace(',', '') + if len(item) > maxw: + maxw = len(item) + intr.append(item) + + maxw = len('INTR_') + maxw + idx = 1 + for i in intr: + s = 'INTR_' + i.upper() + print '%s = %d' % (s.ljust(maxw), idx) + idx += 1 + +gen(sys.argv[1])