From 95cef744801e8c28b25a00aa0d41524976c88b88 Mon Sep 17 00:00:00 2001 From: "mdevan.foobar" Date: Fri, 21 Nov 2008 12:17:42 +0000 Subject: [PATCH] Migrated to LLVM 2.4. git-svn-id: http://llvm-py.googlecode.com/svn/trunk@50 8d1e9007-1d4e-0410-b67e-1979fd6579aa --- CHANGELOG | 5 + README | 12 +- llvm/_core.c | 32 +- llvm/core.py | 1204 ++++++++++++++++++++++++----------------------- llvm/extra.cpp | 24 +- llvm/extra.h | 5 +- llvm/passes.py | 4 +- setup.py | 31 +- test/testall.py | 16 +- 9 files changed, 699 insertions(+), 634 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 0f201cf..46f7e02 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,4 +1,9 @@ +0,5, in progress: + + * Migrate to LLVM 2.4. + + 0.4, 21-Nov-2008: * Code cleanup, added license headers. diff --git a/README b/README index 6ef4275..aed7e30 100644 --- a/README +++ b/README @@ -12,21 +12,19 @@ Home page: Versions: --------- - -This package will work only with LLVM 2.3 release version. If you need llvm-py -for the in-progress LLVM version (2.4), you've to get llvm-py from the SVN -repository -- see the website for more details. + This package will work only with LLVM 2.4 release version. If you need + llvm-py for LLVM 2.3, use the 0.4 version of llvm-py. Quickstart: ----------- - 1. Get 2.3 version of LLVM, build it. Make sure '--enable-pic' is passed to + 1. Get 2.4 version of LLVM, build it. Make sure '--enable-pic' is passed to LLVM's 'configure'. 2. Unpack llvm-py, build and install: - $ tar jxvf llvm-py-0.4.tar.bz2 - $ cd llvm-py-0.4 + $ tar jxvf llvm-py-0.5.tar.bz2 + $ cd llvm-py-0.5 # Locate llvm-config, usually under /Release/bin $ sudo python setup.py install --llvm-config=/path/to/llvm-config diff --git a/llvm/_core.c b/llvm/_core.c index 1a03824..a98c239 100644 --- a/llvm/_core.c +++ b/llvm/_core.c @@ -453,8 +453,8 @@ _wrap_obj2none(LLVMDeleteFunction, LLVMValueRef) _wrap_obj2obj(LLVMGetIntrinsicID, LLVMValueRef, int) _wrap_obj2obj(LLVMGetFunctionCallConv, LLVMValueRef, int) _wrap_objint2none(LLVMSetFunctionCallConv, LLVMValueRef) -_wrap_obj2str(LLVMGetCollector, LLVMValueRef) -_wrap_objstr2none(LLVMSetCollector, LLVMValueRef) +_wrap_obj2str(LLVMGetGC, LLVMValueRef) +_wrap_objstr2none(LLVMSetGC, LLVMValueRef) _wrap_obj2none(LLVMViewFunctionCFG, LLVMValueRef) _wrap_obj2none(LLVMViewFunctionCFGOnly, LLVMValueRef) @@ -476,8 +476,8 @@ _wrap_obj2obj(LLVMCountParams, LLVMValueRef, int) _wrap_obj2obj(LLVMGetFirstParam, LLVMValueRef, LLVMValueRef) _wrap_obj2obj(LLVMGetNextParam, LLVMValueRef, LLVMValueRef) _wrap_obj2obj(LLVMGetParamParent, LLVMValueRef, LLVMValueRef) -_wrap_objint2none(LLVMAddParamAttr, LLVMValueRef) -_wrap_objint2none(LLVMRemoveParamAttr, LLVMValueRef) +_wrap_objint2none(LLVMAddAttribute, LLVMValueRef) +_wrap_objint2none(LLVMRemoveAttribute, LLVMValueRef) _wrap_objint2none(LLVMSetParamAlignment, LLVMValueRef) /*===-- Basic Blocks -----------------------------------------------------===*/ @@ -513,8 +513,8 @@ _wrap_obj2str(LLVMInstGetOpcodeName, LLVMValueRef) _wrap_objint2none(LLVMSetInstructionCallConv, LLVMValueRef) _wrap_obj2obj(LLVMGetInstructionCallConv, LLVMValueRef, int) -_wrap_objintint2none(LLVMAddInstrParamAttr, LLVMValueRef) -_wrap_objintint2none(LLVMRemoveInstrParamAttr, LLVMValueRef) +_wrap_objintint2none(LLVMAddInstrAttribute, LLVMValueRef) +_wrap_objintint2none(LLVMRemoveInstrAttribute, LLVMValueRef) _wrap_objintint2none(LLVMSetInstrParamAlignment, LLVMValueRef) /*===-- PHI Nodes --------------------------------------------------------===*/ @@ -737,7 +737,7 @@ _wrap_pass( DeadArgElimination ) _wrap_pass( DeadTypeElimination ) _wrap_pass( DeadInstElimination ) _wrap_pass( DeadStoreElimination ) -_wrap_pass( GCSE ) +/* _wrap_pass( GCSE ): removed in LLVM 2.4. */ _wrap_pass( GlobalDCE ) _wrap_pass( GlobalOptimizer ) _wrap_pass( GVN ) @@ -837,7 +837,7 @@ _wLLVMCreateExecutionEngine(PyObject *self, PyObject *args) if (force_interpreter) error = LLVMCreateInterpreter(&ee, mp, &outmsg); else - error = LLVMCreateJITCompiler(&ee, mp, &outmsg); + error = LLVMCreateJITCompiler(&ee, mp, 1 /*fast*/, &outmsg); if (error) { ret = PyString_FromString(outmsg); @@ -1174,9 +1174,9 @@ static PyMethodDef core_methods[] = { _method( LLVMDeleteFunction ) _method( LLVMGetIntrinsicID ) _method( LLVMGetFunctionCallConv ) - _method( LLVMSetFunctionCallConv ) - _method( LLVMGetCollector ) - _method( LLVMSetCollector ) + _method( LLVMSetFunctionCallConv ) + _method( LLVMGetGC ) + _method( LLVMSetGC ) _method( LLVMVerifyFunction ) _method( LLVMViewFunctionCFG ) _method( LLVMViewFunctionCFGOnly ) @@ -1186,8 +1186,8 @@ static PyMethodDef core_methods[] = { _method( LLVMGetFirstParam ) _method( LLVMGetNextParam ) _method( LLVMGetParamParent ) - _method( LLVMAddParamAttr ) - _method( LLVMRemoveParamAttr ) + _method( LLVMAddAttribute ) + _method( LLVMRemoveAttribute ) _method( LLVMSetParamAlignment ) /* Basic Blocks */ @@ -1219,8 +1219,8 @@ static PyMethodDef core_methods[] = { /* Call Sites (Call or Invoke) */ _method( LLVMSetInstructionCallConv ) _method( LLVMGetInstructionCallConv ) - _method( LLVMAddInstrParamAttr ) - _method( LLVMRemoveInstrParamAttr ) + _method( LLVMAddInstrAttribute ) + _method( LLVMRemoveInstrAttribute ) _method( LLVMSetInstrParamAlignment ) /* PHI Nodes */ @@ -1343,7 +1343,7 @@ static PyMethodDef core_methods[] = { _pass( DeadTypeElimination ) _pass( DeadInstElimination ) _pass( DeadStoreElimination ) - _pass( GCSE ) + /* _pass( GCSE ): removed in LLVM 2.4. */ _pass( GlobalDCE ) _pass( GlobalOptimizer ) _pass( GVN ) diff --git a/llvm/core.py b/llvm/core.py index de8f5e9..8e8946b 100644 --- a/llvm/core.py +++ b/llvm/core.py @@ -126,600 +126,604 @@ ATTR_READ_NONE = 512 ATTR_READONLY = 1024 # intrinsic IDs -INTR_ANNOTATION = 1 -INTR_ARM_THREAD_POINTER = 2 -INTR_ATOMIC_LAS = 3 -INTR_ATOMIC_LCS = 4 -INTR_ATOMIC_LOAD_AND = 5 -INTR_ATOMIC_LOAD_MAX = 6 -INTR_ATOMIC_LOAD_MIN = 7 -INTR_ATOMIC_LOAD_OR = 8 -INTR_ATOMIC_LOAD_UMAX = 9 -INTR_ATOMIC_LOAD_UMIN = 10 -INTR_ATOMIC_LOAD_XOR = 11 -INTR_ATOMIC_LSS = 12 -INTR_ATOMIC_SWAP = 13 -INTR_BSWAP = 14 -INTR_COS = 15 -INTR_CTLZ = 16 -INTR_CTPOP = 17 -INTR_CTTZ = 18 -INTR_DBG_DECLARE = 19 -INTR_DBG_FUNC_START = 20 -INTR_DBG_REGION_END = 21 -INTR_DBG_REGION_START = 22 -INTR_DBG_STOPPOINT = 23 -INTR_EH_DWARF_CFA = 24 -INTR_EH_EXCEPTION = 25 -INTR_EH_RETURN = 26 -INTR_EH_SELECTOR_I32 = 27 -INTR_EH_SELECTOR_I64 = 28 -INTR_EH_TYPEID_FOR_I32 = 29 -INTR_EH_TYPEID_FOR_I64 = 30 -INTR_EH_UNWIND_INIT = 31 -INTR_FLT_ROUNDS = 32 -INTR_FRAMEADDRESS = 33 -INTR_GCREAD = 34 -INTR_GCROOT = 35 -INTR_GCWRITE = 36 -INTR_INIT_TRAMPOLINE = 37 -INTR_LONGJMP = 38 -INTR_MEMCPY_I32 = 39 -INTR_MEMCPY_I64 = 40 -INTR_MEMMOVE_I32 = 41 -INTR_MEMMOVE_I64 = 42 -INTR_MEMORY_BARRIER = 43 -INTR_MEMSET_I32 = 44 -INTR_MEMSET_I64 = 45 -INTR_PART_SELECT = 46 -INTR_PART_SET = 47 -INTR_PCMARKER = 48 -INTR_POW = 49 -INTR_POWI = 50 -INTR_PPC_ALTIVEC_DSS = 51 -INTR_PPC_ALTIVEC_DSSALL = 52 -INTR_PPC_ALTIVEC_DST = 53 -INTR_PPC_ALTIVEC_DSTST = 54 -INTR_PPC_ALTIVEC_DSTSTT = 55 -INTR_PPC_ALTIVEC_DSTT = 56 -INTR_PPC_ALTIVEC_LVEBX = 57 -INTR_PPC_ALTIVEC_LVEHX = 58 -INTR_PPC_ALTIVEC_LVEWX = 59 -INTR_PPC_ALTIVEC_LVSL = 60 -INTR_PPC_ALTIVEC_LVSR = 61 -INTR_PPC_ALTIVEC_LVX = 62 -INTR_PPC_ALTIVEC_LVXL = 63 -INTR_PPC_ALTIVEC_MFVSCR = 64 -INTR_PPC_ALTIVEC_MTVSCR = 65 -INTR_PPC_ALTIVEC_STVEBX = 66 -INTR_PPC_ALTIVEC_STVEHX = 67 -INTR_PPC_ALTIVEC_STVEWX = 68 -INTR_PPC_ALTIVEC_STVX = 69 -INTR_PPC_ALTIVEC_STVXL = 70 -INTR_PPC_ALTIVEC_VADDCUW = 71 -INTR_PPC_ALTIVEC_VADDSBS = 72 -INTR_PPC_ALTIVEC_VADDSHS = 73 -INTR_PPC_ALTIVEC_VADDSWS = 74 -INTR_PPC_ALTIVEC_VADDUBS = 75 -INTR_PPC_ALTIVEC_VADDUHS = 76 -INTR_PPC_ALTIVEC_VADDUWS = 77 -INTR_PPC_ALTIVEC_VAVGSB = 78 -INTR_PPC_ALTIVEC_VAVGSH = 79 -INTR_PPC_ALTIVEC_VAVGSW = 80 -INTR_PPC_ALTIVEC_VAVGUB = 81 -INTR_PPC_ALTIVEC_VAVGUH = 82 -INTR_PPC_ALTIVEC_VAVGUW = 83 -INTR_PPC_ALTIVEC_VCFSX = 84 -INTR_PPC_ALTIVEC_VCFUX = 85 -INTR_PPC_ALTIVEC_VCMPBFP = 86 -INTR_PPC_ALTIVEC_VCMPBFP_P = 87 -INTR_PPC_ALTIVEC_VCMPEQFP = 88 -INTR_PPC_ALTIVEC_VCMPEQFP_P = 89 -INTR_PPC_ALTIVEC_VCMPEQUB = 90 -INTR_PPC_ALTIVEC_VCMPEQUB_P = 91 -INTR_PPC_ALTIVEC_VCMPEQUH = 92 -INTR_PPC_ALTIVEC_VCMPEQUH_P = 93 -INTR_PPC_ALTIVEC_VCMPEQUW = 94 -INTR_PPC_ALTIVEC_VCMPEQUW_P = 95 -INTR_PPC_ALTIVEC_VCMPGEFP = 96 -INTR_PPC_ALTIVEC_VCMPGEFP_P = 97 -INTR_PPC_ALTIVEC_VCMPGTFP = 98 -INTR_PPC_ALTIVEC_VCMPGTFP_P = 99 -INTR_PPC_ALTIVEC_VCMPGTSB = 100 -INTR_PPC_ALTIVEC_VCMPGTSB_P = 101 -INTR_PPC_ALTIVEC_VCMPGTSH = 102 -INTR_PPC_ALTIVEC_VCMPGTSH_P = 103 -INTR_PPC_ALTIVEC_VCMPGTSW = 104 -INTR_PPC_ALTIVEC_VCMPGTSW_P = 105 -INTR_PPC_ALTIVEC_VCMPGTUB = 106 -INTR_PPC_ALTIVEC_VCMPGTUB_P = 107 -INTR_PPC_ALTIVEC_VCMPGTUH = 108 -INTR_PPC_ALTIVEC_VCMPGTUH_P = 109 -INTR_PPC_ALTIVEC_VCMPGTUW = 110 -INTR_PPC_ALTIVEC_VCMPGTUW_P = 111 -INTR_PPC_ALTIVEC_VCTSXS = 112 -INTR_PPC_ALTIVEC_VCTUXS = 113 -INTR_PPC_ALTIVEC_VEXPTEFP = 114 -INTR_PPC_ALTIVEC_VLOGEFP = 115 -INTR_PPC_ALTIVEC_VMADDFP = 116 -INTR_PPC_ALTIVEC_VMAXFP = 117 -INTR_PPC_ALTIVEC_VMAXSB = 118 -INTR_PPC_ALTIVEC_VMAXSH = 119 -INTR_PPC_ALTIVEC_VMAXSW = 120 -INTR_PPC_ALTIVEC_VMAXUB = 121 -INTR_PPC_ALTIVEC_VMAXUH = 122 -INTR_PPC_ALTIVEC_VMAXUW = 123 -INTR_PPC_ALTIVEC_VMHADDSHS = 124 -INTR_PPC_ALTIVEC_VMHRADDSHS = 125 -INTR_PPC_ALTIVEC_VMINFP = 126 -INTR_PPC_ALTIVEC_VMINSB = 127 -INTR_PPC_ALTIVEC_VMINSH = 128 -INTR_PPC_ALTIVEC_VMINSW = 129 -INTR_PPC_ALTIVEC_VMINUB = 130 -INTR_PPC_ALTIVEC_VMINUH = 131 -INTR_PPC_ALTIVEC_VMINUW = 132 -INTR_PPC_ALTIVEC_VMLADDUHM = 133 -INTR_PPC_ALTIVEC_VMSUMMBM = 134 -INTR_PPC_ALTIVEC_VMSUMSHM = 135 -INTR_PPC_ALTIVEC_VMSUMSHS = 136 -INTR_PPC_ALTIVEC_VMSUMUBM = 137 -INTR_PPC_ALTIVEC_VMSUMUHM = 138 -INTR_PPC_ALTIVEC_VMSUMUHS = 139 -INTR_PPC_ALTIVEC_VMULESB = 140 -INTR_PPC_ALTIVEC_VMULESH = 141 -INTR_PPC_ALTIVEC_VMULEUB = 142 -INTR_PPC_ALTIVEC_VMULEUH = 143 -INTR_PPC_ALTIVEC_VMULOSB = 144 -INTR_PPC_ALTIVEC_VMULOSH = 145 -INTR_PPC_ALTIVEC_VMULOUB = 146 -INTR_PPC_ALTIVEC_VMULOUH = 147 -INTR_PPC_ALTIVEC_VNMSUBFP = 148 -INTR_PPC_ALTIVEC_VPERM = 149 -INTR_PPC_ALTIVEC_VPKPX = 150 -INTR_PPC_ALTIVEC_VPKSHSS = 151 -INTR_PPC_ALTIVEC_VPKSHUS = 152 -INTR_PPC_ALTIVEC_VPKSWSS = 153 -INTR_PPC_ALTIVEC_VPKSWUS = 154 -INTR_PPC_ALTIVEC_VPKUHUS = 155 -INTR_PPC_ALTIVEC_VPKUWUS = 156 -INTR_PPC_ALTIVEC_VREFP = 157 -INTR_PPC_ALTIVEC_VRFIM = 158 -INTR_PPC_ALTIVEC_VRFIN = 159 -INTR_PPC_ALTIVEC_VRFIP = 160 -INTR_PPC_ALTIVEC_VRFIZ = 161 -INTR_PPC_ALTIVEC_VRLB = 162 -INTR_PPC_ALTIVEC_VRLH = 163 -INTR_PPC_ALTIVEC_VRLW = 164 -INTR_PPC_ALTIVEC_VRSQRTEFP = 165 -INTR_PPC_ALTIVEC_VSEL = 166 -INTR_PPC_ALTIVEC_VSL = 167 -INTR_PPC_ALTIVEC_VSLB = 168 -INTR_PPC_ALTIVEC_VSLH = 169 -INTR_PPC_ALTIVEC_VSLO = 170 -INTR_PPC_ALTIVEC_VSLW = 171 -INTR_PPC_ALTIVEC_VSR = 172 -INTR_PPC_ALTIVEC_VSRAB = 173 -INTR_PPC_ALTIVEC_VSRAH = 174 -INTR_PPC_ALTIVEC_VSRAW = 175 -INTR_PPC_ALTIVEC_VSRB = 176 -INTR_PPC_ALTIVEC_VSRH = 177 -INTR_PPC_ALTIVEC_VSRO = 178 -INTR_PPC_ALTIVEC_VSRW = 179 -INTR_PPC_ALTIVEC_VSUBCUW = 180 -INTR_PPC_ALTIVEC_VSUBSBS = 181 -INTR_PPC_ALTIVEC_VSUBSHS = 182 -INTR_PPC_ALTIVEC_VSUBSWS = 183 -INTR_PPC_ALTIVEC_VSUBUBS = 184 -INTR_PPC_ALTIVEC_VSUBUHS = 185 -INTR_PPC_ALTIVEC_VSUBUWS = 186 -INTR_PPC_ALTIVEC_VSUM2SWS = 187 -INTR_PPC_ALTIVEC_VSUM4SBS = 188 -INTR_PPC_ALTIVEC_VSUM4SHS = 189 -INTR_PPC_ALTIVEC_VSUM4UBS = 190 -INTR_PPC_ALTIVEC_VSUMSWS = 191 -INTR_PPC_ALTIVEC_VUPKHPX = 192 -INTR_PPC_ALTIVEC_VUPKHSB = 193 -INTR_PPC_ALTIVEC_VUPKHSH = 194 -INTR_PPC_ALTIVEC_VUPKLPX = 195 -INTR_PPC_ALTIVEC_VUPKLSB = 196 -INTR_PPC_ALTIVEC_VUPKLSH = 197 -INTR_PPC_DCBA = 198 -INTR_PPC_DCBF = 199 -INTR_PPC_DCBI = 200 -INTR_PPC_DCBST = 201 -INTR_PPC_DCBT = 202 -INTR_PPC_DCBTST = 203 -INTR_PPC_DCBZ = 204 -INTR_PPC_DCBZL = 205 -INTR_PREFETCH = 206 -INTR_READCYCLECOUNTER = 207 -INTR_RETURNADDRESS = 208 -INTR_SETJMP = 209 -INTR_SIGLONGJMP = 210 -INTR_SIGSETJMP = 211 -INTR_SIN = 212 -INTR_SPU_SI_A = 213 -INTR_SPU_SI_ADDX = 214 -INTR_SPU_SI_AH = 215 -INTR_SPU_SI_AHI = 216 -INTR_SPU_SI_AI = 217 -INTR_SPU_SI_AND = 218 -INTR_SPU_SI_ANDBI = 219 -INTR_SPU_SI_ANDC = 220 -INTR_SPU_SI_ANDHI = 221 -INTR_SPU_SI_ANDI = 222 -INTR_SPU_SI_BG = 223 -INTR_SPU_SI_BGX = 224 -INTR_SPU_SI_CEQ = 225 -INTR_SPU_SI_CEQB = 226 -INTR_SPU_SI_CEQBI = 227 -INTR_SPU_SI_CEQH = 228 -INTR_SPU_SI_CEQHI = 229 -INTR_SPU_SI_CEQI = 230 -INTR_SPU_SI_CG = 231 -INTR_SPU_SI_CGT = 232 -INTR_SPU_SI_CGTB = 233 -INTR_SPU_SI_CGTBI = 234 -INTR_SPU_SI_CGTH = 235 -INTR_SPU_SI_CGTHI = 236 -INTR_SPU_SI_CGTI = 237 -INTR_SPU_SI_CGX = 238 -INTR_SPU_SI_CLGT = 239 -INTR_SPU_SI_CLGTB = 240 -INTR_SPU_SI_CLGTBI = 241 -INTR_SPU_SI_CLGTH = 242 -INTR_SPU_SI_CLGTHI = 243 -INTR_SPU_SI_CLGTI = 244 -INTR_SPU_SI_DFA = 245 -INTR_SPU_SI_DFM = 246 -INTR_SPU_SI_DFMA = 247 -INTR_SPU_SI_DFMS = 248 -INTR_SPU_SI_DFNMA = 249 -INTR_SPU_SI_DFNMS = 250 -INTR_SPU_SI_DFS = 251 -INTR_SPU_SI_FA = 252 -INTR_SPU_SI_FCEQ = 253 -INTR_SPU_SI_FCGT = 254 -INTR_SPU_SI_FCMEQ = 255 -INTR_SPU_SI_FCMGT = 256 -INTR_SPU_SI_FM = 257 -INTR_SPU_SI_FMA = 258 -INTR_SPU_SI_FMS = 259 -INTR_SPU_SI_FNMS = 260 -INTR_SPU_SI_FS = 261 -INTR_SPU_SI_FSMBI = 262 -INTR_SPU_SI_MPY = 263 -INTR_SPU_SI_MPYA = 264 -INTR_SPU_SI_MPYH = 265 -INTR_SPU_SI_MPYHH = 266 -INTR_SPU_SI_MPYHHA = 267 -INTR_SPU_SI_MPYHHAU = 268 -INTR_SPU_SI_MPYHHU = 269 -INTR_SPU_SI_MPYI = 270 -INTR_SPU_SI_MPYS = 271 -INTR_SPU_SI_MPYU = 272 -INTR_SPU_SI_MPYUI = 273 -INTR_SPU_SI_NAND = 274 -INTR_SPU_SI_NOR = 275 -INTR_SPU_SI_OR = 276 -INTR_SPU_SI_ORBI = 277 -INTR_SPU_SI_ORC = 278 -INTR_SPU_SI_ORHI = 279 -INTR_SPU_SI_ORI = 280 -INTR_SPU_SI_SF = 281 -INTR_SPU_SI_SFH = 282 -INTR_SPU_SI_SFHI = 283 -INTR_SPU_SI_SFI = 284 -INTR_SPU_SI_SFX = 285 -INTR_SPU_SI_SHLI = 286 -INTR_SPU_SI_SHLQBI = 287 -INTR_SPU_SI_SHLQBII = 288 -INTR_SPU_SI_SHLQBY = 289 -INTR_SPU_SI_SHLQBYI = 290 -INTR_SPU_SI_XOR = 291 -INTR_SPU_SI_XORBI = 292 -INTR_SPU_SI_XORHI = 293 -INTR_SPU_SI_XORI = 294 -INTR_SQRT = 295 -INTR_STACKRESTORE = 296 -INTR_STACKSAVE = 297 -INTR_TRAP = 298 -INTR_VACOPY = 299 -INTR_VAEND = 300 -INTR_VAR_ANNOTATION = 301 -INTR_VASTART = 302 -INTR_X86_MMX_EMMS = 303 -INTR_X86_MMX_FEMMS = 304 -INTR_X86_MMX_MASKMOVQ = 305 -INTR_X86_MMX_MOVNT_DQ = 306 -INTR_X86_MMX_PACKSSDW = 307 -INTR_X86_MMX_PACKSSWB = 308 -INTR_X86_MMX_PACKUSWB = 309 -INTR_X86_MMX_PADDS_B = 310 -INTR_X86_MMX_PADDS_W = 311 -INTR_X86_MMX_PADDUS_B = 312 -INTR_X86_MMX_PADDUS_W = 313 -INTR_X86_MMX_PAVG_B = 314 -INTR_X86_MMX_PAVG_W = 315 -INTR_X86_MMX_PCMPEQ_B = 316 -INTR_X86_MMX_PCMPEQ_D = 317 -INTR_X86_MMX_PCMPEQ_W = 318 -INTR_X86_MMX_PCMPGT_B = 319 -INTR_X86_MMX_PCMPGT_D = 320 -INTR_X86_MMX_PCMPGT_W = 321 -INTR_X86_MMX_PMADD_WD = 322 -INTR_X86_MMX_PMAXS_W = 323 -INTR_X86_MMX_PMAXU_B = 324 -INTR_X86_MMX_PMINS_W = 325 -INTR_X86_MMX_PMINU_B = 326 -INTR_X86_MMX_PMOVMSKB = 327 -INTR_X86_MMX_PMULH_W = 328 -INTR_X86_MMX_PMULHU_W = 329 -INTR_X86_MMX_PMULU_DQ = 330 -INTR_X86_MMX_PSAD_BW = 331 -INTR_X86_MMX_PSLL_D = 332 -INTR_X86_MMX_PSLL_Q = 333 -INTR_X86_MMX_PSLL_W = 334 -INTR_X86_MMX_PSLLI_D = 335 -INTR_X86_MMX_PSLLI_Q = 336 -INTR_X86_MMX_PSLLI_W = 337 -INTR_X86_MMX_PSRA_D = 338 -INTR_X86_MMX_PSRA_W = 339 -INTR_X86_MMX_PSRAI_D = 340 -INTR_X86_MMX_PSRAI_W = 341 -INTR_X86_MMX_PSRL_D = 342 -INTR_X86_MMX_PSRL_Q = 343 -INTR_X86_MMX_PSRL_W = 344 -INTR_X86_MMX_PSRLI_D = 345 -INTR_X86_MMX_PSRLI_Q = 346 -INTR_X86_MMX_PSRLI_W = 347 -INTR_X86_MMX_PSUBS_B = 348 -INTR_X86_MMX_PSUBS_W = 349 -INTR_X86_MMX_PSUBUS_B = 350 -INTR_X86_MMX_PSUBUS_W = 351 -INTR_X86_SSE2_ADD_SD = 352 -INTR_X86_SSE2_CLFLUSH = 353 -INTR_X86_SSE2_CMP_PD = 354 -INTR_X86_SSE2_CMP_SD = 355 -INTR_X86_SSE2_COMIEQ_SD = 356 -INTR_X86_SSE2_COMIGE_SD = 357 -INTR_X86_SSE2_COMIGT_SD = 358 -INTR_X86_SSE2_COMILE_SD = 359 -INTR_X86_SSE2_COMILT_SD = 360 -INTR_X86_SSE2_COMINEQ_SD = 361 -INTR_X86_SSE2_CVTDQ2PD = 362 -INTR_X86_SSE2_CVTDQ2PS = 363 -INTR_X86_SSE2_CVTPD2DQ = 364 -INTR_X86_SSE2_CVTPD2PS = 365 -INTR_X86_SSE2_CVTPS2DQ = 366 -INTR_X86_SSE2_CVTPS2PD = 367 -INTR_X86_SSE2_CVTSD2SI = 368 -INTR_X86_SSE2_CVTSD2SI64 = 369 -INTR_X86_SSE2_CVTSD2SS = 370 -INTR_X86_SSE2_CVTSI2SD = 371 -INTR_X86_SSE2_CVTSI642SD = 372 -INTR_X86_SSE2_CVTSS2SD = 373 -INTR_X86_SSE2_CVTTPD2DQ = 374 -INTR_X86_SSE2_CVTTPS2DQ = 375 -INTR_X86_SSE2_CVTTSD2SI = 376 -INTR_X86_SSE2_CVTTSD2SI64 = 377 -INTR_X86_SSE2_DIV_SD = 378 -INTR_X86_SSE2_LFENCE = 379 -INTR_X86_SSE2_LOADH_PD = 380 -INTR_X86_SSE2_LOADL_PD = 381 -INTR_X86_SSE2_LOADU_DQ = 382 -INTR_X86_SSE2_LOADU_PD = 383 -INTR_X86_SSE2_MASKMOV_DQU = 384 -INTR_X86_SSE2_MAX_PD = 385 -INTR_X86_SSE2_MAX_SD = 386 -INTR_X86_SSE2_MFENCE = 387 -INTR_X86_SSE2_MIN_PD = 388 -INTR_X86_SSE2_MIN_SD = 389 -INTR_X86_SSE2_MOVMSK_PD = 390 -INTR_X86_SSE2_MOVNT_DQ = 391 -INTR_X86_SSE2_MOVNT_I = 392 -INTR_X86_SSE2_MOVNT_PD = 393 -INTR_X86_SSE2_MOVS_D = 394 -INTR_X86_SSE2_MUL_SD = 395 -INTR_X86_SSE2_PACKSSDW_128 = 396 -INTR_X86_SSE2_PACKSSWB_128 = 397 -INTR_X86_SSE2_PACKUSWB_128 = 398 -INTR_X86_SSE2_PADDS_B = 399 -INTR_X86_SSE2_PADDS_W = 400 -INTR_X86_SSE2_PADDUS_B = 401 -INTR_X86_SSE2_PADDUS_W = 402 -INTR_X86_SSE2_PAVG_B = 403 -INTR_X86_SSE2_PAVG_W = 404 -INTR_X86_SSE2_PCMPEQ_B = 405 -INTR_X86_SSE2_PCMPEQ_D = 406 -INTR_X86_SSE2_PCMPEQ_W = 407 -INTR_X86_SSE2_PCMPGT_B = 408 -INTR_X86_SSE2_PCMPGT_D = 409 -INTR_X86_SSE2_PCMPGT_W = 410 -INTR_X86_SSE2_PMADD_WD = 411 -INTR_X86_SSE2_PMAXS_W = 412 -INTR_X86_SSE2_PMAXU_B = 413 -INTR_X86_SSE2_PMINS_W = 414 -INTR_X86_SSE2_PMINU_B = 415 -INTR_X86_SSE2_PMOVMSKB_128 = 416 -INTR_X86_SSE2_PMULH_W = 417 -INTR_X86_SSE2_PMULHU_W = 418 -INTR_X86_SSE2_PMULU_DQ = 419 -INTR_X86_SSE2_PSAD_BW = 420 -INTR_X86_SSE2_PSLL_D = 421 -INTR_X86_SSE2_PSLL_DQ = 422 -INTR_X86_SSE2_PSLL_Q = 423 -INTR_X86_SSE2_PSLL_W = 424 -INTR_X86_SSE2_PSLLI_D = 425 -INTR_X86_SSE2_PSLLI_Q = 426 -INTR_X86_SSE2_PSLLI_W = 427 -INTR_X86_SSE2_PSRA_D = 428 -INTR_X86_SSE2_PSRA_W = 429 -INTR_X86_SSE2_PSRAI_D = 430 -INTR_X86_SSE2_PSRAI_W = 431 -INTR_X86_SSE2_PSRL_D = 432 -INTR_X86_SSE2_PSRL_DQ = 433 -INTR_X86_SSE2_PSRL_Q = 434 -INTR_X86_SSE2_PSRL_W = 435 -INTR_X86_SSE2_PSRLI_D = 436 -INTR_X86_SSE2_PSRLI_Q = 437 -INTR_X86_SSE2_PSRLI_W = 438 -INTR_X86_SSE2_PSUBS_B = 439 -INTR_X86_SSE2_PSUBS_W = 440 -INTR_X86_SSE2_PSUBUS_B = 441 -INTR_X86_SSE2_PSUBUS_W = 442 -INTR_X86_SSE2_PUNPCKH_QDQ = 443 -INTR_X86_SSE2_PUNPCKL_QDQ = 444 -INTR_X86_SSE2_SHUF_PD = 445 -INTR_X86_SSE2_SQRT_PD = 446 -INTR_X86_SSE2_SQRT_SD = 447 -INTR_X86_SSE2_STOREL_DQ = 448 -INTR_X86_SSE2_STOREU_DQ = 449 -INTR_X86_SSE2_STOREU_PD = 450 -INTR_X86_SSE2_SUB_SD = 451 -INTR_X86_SSE2_UCOMIEQ_SD = 452 -INTR_X86_SSE2_UCOMIGE_SD = 453 -INTR_X86_SSE2_UCOMIGT_SD = 454 -INTR_X86_SSE2_UCOMILE_SD = 455 -INTR_X86_SSE2_UCOMILT_SD = 456 -INTR_X86_SSE2_UCOMINEQ_SD = 457 -INTR_X86_SSE2_UNPCKH_PD = 458 -INTR_X86_SSE2_UNPCKL_PD = 459 -INTR_X86_SSE3_ADDSUB_PD = 460 -INTR_X86_SSE3_ADDSUB_PS = 461 -INTR_X86_SSE3_HADD_PD = 462 -INTR_X86_SSE3_HADD_PS = 463 -INTR_X86_SSE3_HSUB_PD = 464 -INTR_X86_SSE3_HSUB_PS = 465 -INTR_X86_SSE3_LDU_DQ = 466 -INTR_X86_SSE3_MONITOR = 467 -INTR_X86_SSE3_MWAIT = 468 -INTR_X86_SSE41_BLENDPD = 469 -INTR_X86_SSE41_BLENDPS = 470 -INTR_X86_SSE41_BLENDVPD = 471 -INTR_X86_SSE41_BLENDVPS = 472 -INTR_X86_SSE41_DPPD = 473 -INTR_X86_SSE41_DPPS = 474 -INTR_X86_SSE41_EXTRACTPS = 475 -INTR_X86_SSE41_INSERTPS = 476 -INTR_X86_SSE41_MOVNTDQA = 477 -INTR_X86_SSE41_MPSADBW = 478 -INTR_X86_SSE41_PACKUSDW = 479 -INTR_X86_SSE41_PBLENDVB = 480 -INTR_X86_SSE41_PBLENDW = 481 -INTR_X86_SSE41_PCMPEQQ = 482 -INTR_X86_SSE41_PEXTRB = 483 -INTR_X86_SSE41_PEXTRD = 484 -INTR_X86_SSE41_PEXTRQ = 485 -INTR_X86_SSE41_PHMINPOSUW = 486 -INTR_X86_SSE41_PINSRB = 487 -INTR_X86_SSE41_PINSRD = 488 -INTR_X86_SSE41_PINSRQ = 489 -INTR_X86_SSE41_PMAXSB = 490 -INTR_X86_SSE41_PMAXSD = 491 -INTR_X86_SSE41_PMAXUD = 492 -INTR_X86_SSE41_PMAXUW = 493 -INTR_X86_SSE41_PMINSB = 494 -INTR_X86_SSE41_PMINSD = 495 -INTR_X86_SSE41_PMINUD = 496 -INTR_X86_SSE41_PMINUW = 497 -INTR_X86_SSE41_PMOVSXBD = 498 -INTR_X86_SSE41_PMOVSXBQ = 499 -INTR_X86_SSE41_PMOVSXBW = 500 -INTR_X86_SSE41_PMOVSXDQ = 501 -INTR_X86_SSE41_PMOVSXWD = 502 -INTR_X86_SSE41_PMOVSXWQ = 503 -INTR_X86_SSE41_PMOVZXBD = 504 -INTR_X86_SSE41_PMOVZXBQ = 505 -INTR_X86_SSE41_PMOVZXBW = 506 -INTR_X86_SSE41_PMOVZXDQ = 507 -INTR_X86_SSE41_PMOVZXWD = 508 -INTR_X86_SSE41_PMOVZXWQ = 509 -INTR_X86_SSE41_PMULDQ = 510 -INTR_X86_SSE41_PMULLD = 511 -INTR_X86_SSE41_ROUND_PD = 512 -INTR_X86_SSE41_ROUND_PS = 513 -INTR_X86_SSE41_ROUND_SD = 514 -INTR_X86_SSE41_ROUND_SS = 515 -INTR_X86_SSE_ADD_SS = 516 -INTR_X86_SSE_CMP_PS = 517 -INTR_X86_SSE_CMP_SS = 518 -INTR_X86_SSE_COMIEQ_SS = 519 -INTR_X86_SSE_COMIGE_SS = 520 -INTR_X86_SSE_COMIGT_SS = 521 -INTR_X86_SSE_COMILE_SS = 522 -INTR_X86_SSE_COMILT_SS = 523 -INTR_X86_SSE_COMINEQ_SS = 524 -INTR_X86_SSE_CVTPD2PI = 525 -INTR_X86_SSE_CVTPI2PD = 526 -INTR_X86_SSE_CVTPI2PS = 527 -INTR_X86_SSE_CVTPS2PI = 528 -INTR_X86_SSE_CVTSI2SS = 529 -INTR_X86_SSE_CVTSI642SS = 530 -INTR_X86_SSE_CVTSS2SI = 531 -INTR_X86_SSE_CVTSS2SI64 = 532 -INTR_X86_SSE_CVTTPD2PI = 533 -INTR_X86_SSE_CVTTPS2PI = 534 -INTR_X86_SSE_CVTTSS2SI = 535 -INTR_X86_SSE_CVTTSS2SI64 = 536 -INTR_X86_SSE_DIV_SS = 537 -INTR_X86_SSE_LDMXCSR = 538 -INTR_X86_SSE_LOADU_PS = 539 -INTR_X86_SSE_MAX_PS = 540 -INTR_X86_SSE_MAX_SS = 541 -INTR_X86_SSE_MIN_PS = 542 -INTR_X86_SSE_MIN_SS = 543 -INTR_X86_SSE_MOVMSK_PS = 544 -INTR_X86_SSE_MOVNT_PS = 545 -INTR_X86_SSE_MUL_SS = 546 -INTR_X86_SSE_RCP_PS = 547 -INTR_X86_SSE_RCP_SS = 548 -INTR_X86_SSE_RSQRT_PS = 549 -INTR_X86_SSE_RSQRT_SS = 550 -INTR_X86_SSE_SFENCE = 551 -INTR_X86_SSE_SQRT_PS = 552 -INTR_X86_SSE_SQRT_SS = 553 -INTR_X86_SSE_STMXCSR = 554 -INTR_X86_SSE_STOREU_PS = 555 -INTR_X86_SSE_SUB_SS = 556 -INTR_X86_SSE_UCOMIEQ_SS = 557 -INTR_X86_SSE_UCOMIGE_SS = 558 -INTR_X86_SSE_UCOMIGT_SS = 559 -INTR_X86_SSE_UCOMILE_SS = 560 -INTR_X86_SSE_UCOMILT_SS = 561 -INTR_X86_SSE_UCOMINEQ_SS = 562 -INTR_X86_SSSE3_PABS_B = 563 -INTR_X86_SSSE3_PABS_B_128 = 564 -INTR_X86_SSSE3_PABS_D = 565 -INTR_X86_SSSE3_PABS_D_128 = 566 -INTR_X86_SSSE3_PABS_W = 567 -INTR_X86_SSSE3_PABS_W_128 = 568 -INTR_X86_SSSE3_PALIGN_R = 569 -INTR_X86_SSSE3_PALIGN_R_128 = 570 -INTR_X86_SSSE3_PHADD_D = 571 -INTR_X86_SSSE3_PHADD_D_128 = 572 -INTR_X86_SSSE3_PHADD_SW = 573 -INTR_X86_SSSE3_PHADD_SW_128 = 574 -INTR_X86_SSSE3_PHADD_W = 575 -INTR_X86_SSSE3_PHADD_W_128 = 576 -INTR_X86_SSSE3_PHSUB_D = 577 -INTR_X86_SSSE3_PHSUB_D_128 = 578 -INTR_X86_SSSE3_PHSUB_SW = 579 -INTR_X86_SSSE3_PHSUB_SW_128 = 580 -INTR_X86_SSSE3_PHSUB_W = 581 -INTR_X86_SSSE3_PHSUB_W_128 = 582 -INTR_X86_SSSE3_PMADD_UB_SW = 583 -INTR_X86_SSSE3_PMADD_UB_SW_128 = 584 -INTR_X86_SSSE3_PMUL_HR_SW = 585 -INTR_X86_SSSE3_PMUL_HR_SW_128 = 586 -INTR_X86_SSSE3_PSHUF_B = 587 -INTR_X86_SSSE3_PSHUF_B_128 = 588 -INTR_X86_SSSE3_PSIGN_B = 589 -INTR_X86_SSSE3_PSIGN_B_128 = 590 -INTR_X86_SSSE3_PSIGN_D = 591 -INTR_X86_SSSE3_PSIGN_D_128 = 592 -INTR_X86_SSSE3_PSIGN_W = 593 -INTR_X86_SSSE3_PSIGN_W_128 = 594 +INTR_ALPHA_UMULH = 1 +INTR_ANNOTATION = 2 +INTR_ARM_THREAD_POINTER = 3 +INTR_ATOMIC_CMP_SWAP = 4 +INTR_ATOMIC_LOAD_ADD = 5 +INTR_ATOMIC_LOAD_AND = 6 +INTR_ATOMIC_LOAD_MAX = 7 +INTR_ATOMIC_LOAD_MIN = 8 +INTR_ATOMIC_LOAD_NAND = 9 +INTR_ATOMIC_LOAD_OR = 10 +INTR_ATOMIC_LOAD_SUB = 11 +INTR_ATOMIC_LOAD_UMAX = 12 +INTR_ATOMIC_LOAD_UMIN = 13 +INTR_ATOMIC_LOAD_XOR = 14 +INTR_ATOMIC_SWAP = 15 +INTR_BSWAP = 16 +INTR_COS = 17 +INTR_CTLZ = 18 +INTR_CTPOP = 19 +INTR_CTTZ = 20 +INTR_DBG_DECLARE = 21 +INTR_DBG_FUNC_START = 22 +INTR_DBG_REGION_END = 23 +INTR_DBG_REGION_START = 24 +INTR_DBG_STOPPOINT = 25 +INTR_EH_DWARF_CFA = 26 +INTR_EH_EXCEPTION = 27 +INTR_EH_RETURN_I32 = 28 +INTR_EH_RETURN_I64 = 29 +INTR_EH_SELECTOR_I32 = 30 +INTR_EH_SELECTOR_I64 = 31 +INTR_EH_TYPEID_FOR_I32 = 32 +INTR_EH_TYPEID_FOR_I64 = 33 +INTR_EH_UNWIND_INIT = 34 +INTR_EXP = 35 +INTR_EXP2 = 36 +INTR_FLT_ROUNDS = 37 +INTR_FRAMEADDRESS = 38 +INTR_GCREAD = 39 +INTR_GCROOT = 40 +INTR_GCWRITE = 41 +INTR_INIT_TRAMPOLINE = 42 +INTR_LOG = 43 +INTR_LOG10 = 44 +INTR_LOG2 = 45 +INTR_LONGJMP = 46 +INTR_MEMCPY_I32 = 47 +INTR_MEMCPY_I64 = 48 +INTR_MEMMOVE_I32 = 49 +INTR_MEMMOVE_I64 = 50 +INTR_MEMORY_BARRIER = 51 +INTR_MEMSET_I32 = 52 +INTR_MEMSET_I64 = 53 +INTR_PART_SELECT = 54 +INTR_PART_SET = 55 +INTR_PCMARKER = 56 +INTR_POW = 57 +INTR_POWI = 58 +INTR_PPC_ALTIVEC_DSS = 59 +INTR_PPC_ALTIVEC_DSSALL = 60 +INTR_PPC_ALTIVEC_DST = 61 +INTR_PPC_ALTIVEC_DSTST = 62 +INTR_PPC_ALTIVEC_DSTSTT = 63 +INTR_PPC_ALTIVEC_DSTT = 64 +INTR_PPC_ALTIVEC_LVEBX = 65 +INTR_PPC_ALTIVEC_LVEHX = 66 +INTR_PPC_ALTIVEC_LVEWX = 67 +INTR_PPC_ALTIVEC_LVSL = 68 +INTR_PPC_ALTIVEC_LVSR = 69 +INTR_PPC_ALTIVEC_LVX = 70 +INTR_PPC_ALTIVEC_LVXL = 71 +INTR_PPC_ALTIVEC_MFVSCR = 72 +INTR_PPC_ALTIVEC_MTVSCR = 73 +INTR_PPC_ALTIVEC_STVEBX = 74 +INTR_PPC_ALTIVEC_STVEHX = 75 +INTR_PPC_ALTIVEC_STVEWX = 76 +INTR_PPC_ALTIVEC_STVX = 77 +INTR_PPC_ALTIVEC_STVXL = 78 +INTR_PPC_ALTIVEC_VADDCUW = 79 +INTR_PPC_ALTIVEC_VADDSBS = 80 +INTR_PPC_ALTIVEC_VADDSHS = 81 +INTR_PPC_ALTIVEC_VADDSWS = 82 +INTR_PPC_ALTIVEC_VADDUBS = 83 +INTR_PPC_ALTIVEC_VADDUHS = 84 +INTR_PPC_ALTIVEC_VADDUWS = 85 +INTR_PPC_ALTIVEC_VAVGSB = 86 +INTR_PPC_ALTIVEC_VAVGSH = 87 +INTR_PPC_ALTIVEC_VAVGSW = 88 +INTR_PPC_ALTIVEC_VAVGUB = 89 +INTR_PPC_ALTIVEC_VAVGUH = 90 +INTR_PPC_ALTIVEC_VAVGUW = 91 +INTR_PPC_ALTIVEC_VCFSX = 92 +INTR_PPC_ALTIVEC_VCFUX = 93 +INTR_PPC_ALTIVEC_VCMPBFP = 94 +INTR_PPC_ALTIVEC_VCMPBFP_P = 95 +INTR_PPC_ALTIVEC_VCMPEQFP = 96 +INTR_PPC_ALTIVEC_VCMPEQFP_P = 97 +INTR_PPC_ALTIVEC_VCMPEQUB = 98 +INTR_PPC_ALTIVEC_VCMPEQUB_P = 99 +INTR_PPC_ALTIVEC_VCMPEQUH = 100 +INTR_PPC_ALTIVEC_VCMPEQUH_P = 101 +INTR_PPC_ALTIVEC_VCMPEQUW = 102 +INTR_PPC_ALTIVEC_VCMPEQUW_P = 103 +INTR_PPC_ALTIVEC_VCMPGEFP = 104 +INTR_PPC_ALTIVEC_VCMPGEFP_P = 105 +INTR_PPC_ALTIVEC_VCMPGTFP = 106 +INTR_PPC_ALTIVEC_VCMPGTFP_P = 107 +INTR_PPC_ALTIVEC_VCMPGTSB = 108 +INTR_PPC_ALTIVEC_VCMPGTSB_P = 109 +INTR_PPC_ALTIVEC_VCMPGTSH = 110 +INTR_PPC_ALTIVEC_VCMPGTSH_P = 111 +INTR_PPC_ALTIVEC_VCMPGTSW = 112 +INTR_PPC_ALTIVEC_VCMPGTSW_P = 113 +INTR_PPC_ALTIVEC_VCMPGTUB = 114 +INTR_PPC_ALTIVEC_VCMPGTUB_P = 115 +INTR_PPC_ALTIVEC_VCMPGTUH = 116 +INTR_PPC_ALTIVEC_VCMPGTUH_P = 117 +INTR_PPC_ALTIVEC_VCMPGTUW = 118 +INTR_PPC_ALTIVEC_VCMPGTUW_P = 119 +INTR_PPC_ALTIVEC_VCTSXS = 120 +INTR_PPC_ALTIVEC_VCTUXS = 121 +INTR_PPC_ALTIVEC_VEXPTEFP = 122 +INTR_PPC_ALTIVEC_VLOGEFP = 123 +INTR_PPC_ALTIVEC_VMADDFP = 124 +INTR_PPC_ALTIVEC_VMAXFP = 125 +INTR_PPC_ALTIVEC_VMAXSB = 126 +INTR_PPC_ALTIVEC_VMAXSH = 127 +INTR_PPC_ALTIVEC_VMAXSW = 128 +INTR_PPC_ALTIVEC_VMAXUB = 129 +INTR_PPC_ALTIVEC_VMAXUH = 130 +INTR_PPC_ALTIVEC_VMAXUW = 131 +INTR_PPC_ALTIVEC_VMHADDSHS = 132 +INTR_PPC_ALTIVEC_VMHRADDSHS = 133 +INTR_PPC_ALTIVEC_VMINFP = 134 +INTR_PPC_ALTIVEC_VMINSB = 135 +INTR_PPC_ALTIVEC_VMINSH = 136 +INTR_PPC_ALTIVEC_VMINSW = 137 +INTR_PPC_ALTIVEC_VMINUB = 138 +INTR_PPC_ALTIVEC_VMINUH = 139 +INTR_PPC_ALTIVEC_VMINUW = 140 +INTR_PPC_ALTIVEC_VMLADDUHM = 141 +INTR_PPC_ALTIVEC_VMSUMMBM = 142 +INTR_PPC_ALTIVEC_VMSUMSHM = 143 +INTR_PPC_ALTIVEC_VMSUMSHS = 144 +INTR_PPC_ALTIVEC_VMSUMUBM = 145 +INTR_PPC_ALTIVEC_VMSUMUHM = 146 +INTR_PPC_ALTIVEC_VMSUMUHS = 147 +INTR_PPC_ALTIVEC_VMULESB = 148 +INTR_PPC_ALTIVEC_VMULESH = 149 +INTR_PPC_ALTIVEC_VMULEUB = 150 +INTR_PPC_ALTIVEC_VMULEUH = 151 +INTR_PPC_ALTIVEC_VMULOSB = 152 +INTR_PPC_ALTIVEC_VMULOSH = 153 +INTR_PPC_ALTIVEC_VMULOUB = 154 +INTR_PPC_ALTIVEC_VMULOUH = 155 +INTR_PPC_ALTIVEC_VNMSUBFP = 156 +INTR_PPC_ALTIVEC_VPERM = 157 +INTR_PPC_ALTIVEC_VPKPX = 158 +INTR_PPC_ALTIVEC_VPKSHSS = 159 +INTR_PPC_ALTIVEC_VPKSHUS = 160 +INTR_PPC_ALTIVEC_VPKSWSS = 161 +INTR_PPC_ALTIVEC_VPKSWUS = 162 +INTR_PPC_ALTIVEC_VPKUHUS = 163 +INTR_PPC_ALTIVEC_VPKUWUS = 164 +INTR_PPC_ALTIVEC_VREFP = 165 +INTR_PPC_ALTIVEC_VRFIM = 166 +INTR_PPC_ALTIVEC_VRFIN = 167 +INTR_PPC_ALTIVEC_VRFIP = 168 +INTR_PPC_ALTIVEC_VRFIZ = 169 +INTR_PPC_ALTIVEC_VRLB = 170 +INTR_PPC_ALTIVEC_VRLH = 171 +INTR_PPC_ALTIVEC_VRLW = 172 +INTR_PPC_ALTIVEC_VRSQRTEFP = 173 +INTR_PPC_ALTIVEC_VSEL = 174 +INTR_PPC_ALTIVEC_VSL = 175 +INTR_PPC_ALTIVEC_VSLB = 176 +INTR_PPC_ALTIVEC_VSLH = 177 +INTR_PPC_ALTIVEC_VSLO = 178 +INTR_PPC_ALTIVEC_VSLW = 179 +INTR_PPC_ALTIVEC_VSR = 180 +INTR_PPC_ALTIVEC_VSRAB = 181 +INTR_PPC_ALTIVEC_VSRAH = 182 +INTR_PPC_ALTIVEC_VSRAW = 183 +INTR_PPC_ALTIVEC_VSRB = 184 +INTR_PPC_ALTIVEC_VSRH = 185 +INTR_PPC_ALTIVEC_VSRO = 186 +INTR_PPC_ALTIVEC_VSRW = 187 +INTR_PPC_ALTIVEC_VSUBCUW = 188 +INTR_PPC_ALTIVEC_VSUBSBS = 189 +INTR_PPC_ALTIVEC_VSUBSHS = 190 +INTR_PPC_ALTIVEC_VSUBSWS = 191 +INTR_PPC_ALTIVEC_VSUBUBS = 192 +INTR_PPC_ALTIVEC_VSUBUHS = 193 +INTR_PPC_ALTIVEC_VSUBUWS = 194 +INTR_PPC_ALTIVEC_VSUM2SWS = 195 +INTR_PPC_ALTIVEC_VSUM4SBS = 196 +INTR_PPC_ALTIVEC_VSUM4SHS = 197 +INTR_PPC_ALTIVEC_VSUM4UBS = 198 +INTR_PPC_ALTIVEC_VSUMSWS = 199 +INTR_PPC_ALTIVEC_VUPKHPX = 200 +INTR_PPC_ALTIVEC_VUPKHSB = 201 +INTR_PPC_ALTIVEC_VUPKHSH = 202 +INTR_PPC_ALTIVEC_VUPKLPX = 203 +INTR_PPC_ALTIVEC_VUPKLSB = 204 +INTR_PPC_ALTIVEC_VUPKLSH = 205 +INTR_PPC_DCBA = 206 +INTR_PPC_DCBF = 207 +INTR_PPC_DCBI = 208 +INTR_PPC_DCBST = 209 +INTR_PPC_DCBT = 210 +INTR_PPC_DCBTST = 211 +INTR_PPC_DCBZ = 212 +INTR_PPC_DCBZL = 213 +INTR_PPC_SYNC = 214 +INTR_PREFETCH = 215 +INTR_READCYCLECOUNTER = 216 +INTR_RETURNADDRESS = 217 +INTR_SETJMP = 218 +INTR_SIGLONGJMP = 219 +INTR_SIGSETJMP = 220 +INTR_SIN = 221 +INTR_SPU_SI_A = 222 +INTR_SPU_SI_ADDX = 223 +INTR_SPU_SI_AH = 224 +INTR_SPU_SI_AHI = 225 +INTR_SPU_SI_AI = 226 +INTR_SPU_SI_AND = 227 +INTR_SPU_SI_ANDBI = 228 +INTR_SPU_SI_ANDC = 229 +INTR_SPU_SI_ANDHI = 230 +INTR_SPU_SI_ANDI = 231 +INTR_SPU_SI_BG = 232 +INTR_SPU_SI_BGX = 233 +INTR_SPU_SI_CEQ = 234 +INTR_SPU_SI_CEQB = 235 +INTR_SPU_SI_CEQBI = 236 +INTR_SPU_SI_CEQH = 237 +INTR_SPU_SI_CEQHI = 238 +INTR_SPU_SI_CEQI = 239 +INTR_SPU_SI_CG = 240 +INTR_SPU_SI_CGT = 241 +INTR_SPU_SI_CGTB = 242 +INTR_SPU_SI_CGTBI = 243 +INTR_SPU_SI_CGTH = 244 +INTR_SPU_SI_CGTHI = 245 +INTR_SPU_SI_CGTI = 246 +INTR_SPU_SI_CGX = 247 +INTR_SPU_SI_CLGT = 248 +INTR_SPU_SI_CLGTB = 249 +INTR_SPU_SI_CLGTBI = 250 +INTR_SPU_SI_CLGTH = 251 +INTR_SPU_SI_CLGTHI = 252 +INTR_SPU_SI_CLGTI = 253 +INTR_SPU_SI_DFA = 254 +INTR_SPU_SI_DFM = 255 +INTR_SPU_SI_DFMA = 256 +INTR_SPU_SI_DFMS = 257 +INTR_SPU_SI_DFNMA = 258 +INTR_SPU_SI_DFNMS = 259 +INTR_SPU_SI_DFS = 260 +INTR_SPU_SI_FA = 261 +INTR_SPU_SI_FCEQ = 262 +INTR_SPU_SI_FCGT = 263 +INTR_SPU_SI_FCMEQ = 264 +INTR_SPU_SI_FCMGT = 265 +INTR_SPU_SI_FM = 266 +INTR_SPU_SI_FMA = 267 +INTR_SPU_SI_FMS = 268 +INTR_SPU_SI_FNMS = 269 +INTR_SPU_SI_FS = 270 +INTR_SPU_SI_FSMBI = 271 +INTR_SPU_SI_MPY = 272 +INTR_SPU_SI_MPYA = 273 +INTR_SPU_SI_MPYH = 274 +INTR_SPU_SI_MPYHH = 275 +INTR_SPU_SI_MPYHHA = 276 +INTR_SPU_SI_MPYHHAU = 277 +INTR_SPU_SI_MPYHHU = 278 +INTR_SPU_SI_MPYI = 279 +INTR_SPU_SI_MPYS = 280 +INTR_SPU_SI_MPYU = 281 +INTR_SPU_SI_MPYUI = 282 +INTR_SPU_SI_NAND = 283 +INTR_SPU_SI_NOR = 284 +INTR_SPU_SI_OR = 285 +INTR_SPU_SI_ORBI = 286 +INTR_SPU_SI_ORC = 287 +INTR_SPU_SI_ORHI = 288 +INTR_SPU_SI_ORI = 289 +INTR_SPU_SI_SF = 290 +INTR_SPU_SI_SFH = 291 +INTR_SPU_SI_SFHI = 292 +INTR_SPU_SI_SFI = 293 +INTR_SPU_SI_SFX = 294 +INTR_SPU_SI_SHLI = 295 +INTR_SPU_SI_SHLQBI = 296 +INTR_SPU_SI_SHLQBII = 297 +INTR_SPU_SI_SHLQBY = 298 +INTR_SPU_SI_SHLQBYI = 299 +INTR_SPU_SI_XOR = 300 +INTR_SPU_SI_XORBI = 301 +INTR_SPU_SI_XORHI = 302 +INTR_SPU_SI_XORI = 303 +INTR_SQRT = 304 +INTR_STACKRESTORE = 305 +INTR_STACKSAVE = 306 +INTR_TRAP = 307 +INTR_VACOPY = 308 +INTR_VAEND = 309 +INTR_VAR_ANNOTATION = 310 +INTR_VASTART = 311 +INTR_X86_MMX_EMMS = 312 +INTR_X86_MMX_FEMMS = 313 +INTR_X86_MMX_MASKMOVQ = 314 +INTR_X86_MMX_MOVNT_DQ = 315 +INTR_X86_MMX_PACKSSDW = 316 +INTR_X86_MMX_PACKSSWB = 317 +INTR_X86_MMX_PACKUSWB = 318 +INTR_X86_MMX_PADDS_B = 319 +INTR_X86_MMX_PADDS_W = 320 +INTR_X86_MMX_PADDUS_B = 321 +INTR_X86_MMX_PADDUS_W = 322 +INTR_X86_MMX_PAVG_B = 323 +INTR_X86_MMX_PAVG_W = 324 +INTR_X86_MMX_PCMPEQ_B = 325 +INTR_X86_MMX_PCMPEQ_D = 326 +INTR_X86_MMX_PCMPEQ_W = 327 +INTR_X86_MMX_PCMPGT_B = 328 +INTR_X86_MMX_PCMPGT_D = 329 +INTR_X86_MMX_PCMPGT_W = 330 +INTR_X86_MMX_PMADD_WD = 331 +INTR_X86_MMX_PMAXS_W = 332 +INTR_X86_MMX_PMAXU_B = 333 +INTR_X86_MMX_PMINS_W = 334 +INTR_X86_MMX_PMINU_B = 335 +INTR_X86_MMX_PMOVMSKB = 336 +INTR_X86_MMX_PMULH_W = 337 +INTR_X86_MMX_PMULHU_W = 338 +INTR_X86_MMX_PMULU_DQ = 339 +INTR_X86_MMX_PSAD_BW = 340 +INTR_X86_MMX_PSLL_D = 341 +INTR_X86_MMX_PSLL_Q = 342 +INTR_X86_MMX_PSLL_W = 343 +INTR_X86_MMX_PSLLI_D = 344 +INTR_X86_MMX_PSLLI_Q = 345 +INTR_X86_MMX_PSLLI_W = 346 +INTR_X86_MMX_PSRA_D = 347 +INTR_X86_MMX_PSRA_W = 348 +INTR_X86_MMX_PSRAI_D = 349 +INTR_X86_MMX_PSRAI_W = 350 +INTR_X86_MMX_PSRL_D = 351 +INTR_X86_MMX_PSRL_Q = 352 +INTR_X86_MMX_PSRL_W = 353 +INTR_X86_MMX_PSRLI_D = 354 +INTR_X86_MMX_PSRLI_Q = 355 +INTR_X86_MMX_PSRLI_W = 356 +INTR_X86_MMX_PSUBS_B = 357 +INTR_X86_MMX_PSUBS_W = 358 +INTR_X86_MMX_PSUBUS_B = 359 +INTR_X86_MMX_PSUBUS_W = 360 +INTR_X86_SSE2_ADD_SD = 361 +INTR_X86_SSE2_CLFLUSH = 362 +INTR_X86_SSE2_CMP_PD = 363 +INTR_X86_SSE2_CMP_SD = 364 +INTR_X86_SSE2_COMIEQ_SD = 365 +INTR_X86_SSE2_COMIGE_SD = 366 +INTR_X86_SSE2_COMIGT_SD = 367 +INTR_X86_SSE2_COMILE_SD = 368 +INTR_X86_SSE2_COMILT_SD = 369 +INTR_X86_SSE2_COMINEQ_SD = 370 +INTR_X86_SSE2_CVTDQ2PD = 371 +INTR_X86_SSE2_CVTDQ2PS = 372 +INTR_X86_SSE2_CVTPD2DQ = 373 +INTR_X86_SSE2_CVTPD2PS = 374 +INTR_X86_SSE2_CVTPS2DQ = 375 +INTR_X86_SSE2_CVTPS2PD = 376 +INTR_X86_SSE2_CVTSD2SI = 377 +INTR_X86_SSE2_CVTSD2SI64 = 378 +INTR_X86_SSE2_CVTSD2SS = 379 +INTR_X86_SSE2_CVTSI2SD = 380 +INTR_X86_SSE2_CVTSI642SD = 381 +INTR_X86_SSE2_CVTSS2SD = 382 +INTR_X86_SSE2_CVTTPD2DQ = 383 +INTR_X86_SSE2_CVTTPS2DQ = 384 +INTR_X86_SSE2_CVTTSD2SI = 385 +INTR_X86_SSE2_CVTTSD2SI64 = 386 +INTR_X86_SSE2_DIV_SD = 387 +INTR_X86_SSE2_LFENCE = 388 +INTR_X86_SSE2_LOADU_DQ = 389 +INTR_X86_SSE2_LOADU_PD = 390 +INTR_X86_SSE2_MASKMOV_DQU = 391 +INTR_X86_SSE2_MAX_PD = 392 +INTR_X86_SSE2_MAX_SD = 393 +INTR_X86_SSE2_MFENCE = 394 +INTR_X86_SSE2_MIN_PD = 395 +INTR_X86_SSE2_MIN_SD = 396 +INTR_X86_SSE2_MOVMSK_PD = 397 +INTR_X86_SSE2_MOVNT_DQ = 398 +INTR_X86_SSE2_MOVNT_I = 399 +INTR_X86_SSE2_MOVNT_PD = 400 +INTR_X86_SSE2_MUL_SD = 401 +INTR_X86_SSE2_PACKSSDW_128 = 402 +INTR_X86_SSE2_PACKSSWB_128 = 403 +INTR_X86_SSE2_PACKUSWB_128 = 404 +INTR_X86_SSE2_PADDS_B = 405 +INTR_X86_SSE2_PADDS_W = 406 +INTR_X86_SSE2_PADDUS_B = 407 +INTR_X86_SSE2_PADDUS_W = 408 +INTR_X86_SSE2_PAVG_B = 409 +INTR_X86_SSE2_PAVG_W = 410 +INTR_X86_SSE2_PCMPEQ_B = 411 +INTR_X86_SSE2_PCMPEQ_D = 412 +INTR_X86_SSE2_PCMPEQ_W = 413 +INTR_X86_SSE2_PCMPGT_B = 414 +INTR_X86_SSE2_PCMPGT_D = 415 +INTR_X86_SSE2_PCMPGT_W = 416 +INTR_X86_SSE2_PMADD_WD = 417 +INTR_X86_SSE2_PMAXS_W = 418 +INTR_X86_SSE2_PMAXU_B = 419 +INTR_X86_SSE2_PMINS_W = 420 +INTR_X86_SSE2_PMINU_B = 421 +INTR_X86_SSE2_PMOVMSKB_128 = 422 +INTR_X86_SSE2_PMULH_W = 423 +INTR_X86_SSE2_PMULHU_W = 424 +INTR_X86_SSE2_PMULU_DQ = 425 +INTR_X86_SSE2_PSAD_BW = 426 +INTR_X86_SSE2_PSLL_D = 427 +INTR_X86_SSE2_PSLL_DQ = 428 +INTR_X86_SSE2_PSLL_DQ_BS = 429 +INTR_X86_SSE2_PSLL_Q = 430 +INTR_X86_SSE2_PSLL_W = 431 +INTR_X86_SSE2_PSLLI_D = 432 +INTR_X86_SSE2_PSLLI_Q = 433 +INTR_X86_SSE2_PSLLI_W = 434 +INTR_X86_SSE2_PSRA_D = 435 +INTR_X86_SSE2_PSRA_W = 436 +INTR_X86_SSE2_PSRAI_D = 437 +INTR_X86_SSE2_PSRAI_W = 438 +INTR_X86_SSE2_PSRL_D = 439 +INTR_X86_SSE2_PSRL_DQ = 440 +INTR_X86_SSE2_PSRL_DQ_BS = 441 +INTR_X86_SSE2_PSRL_Q = 442 +INTR_X86_SSE2_PSRL_W = 443 +INTR_X86_SSE2_PSRLI_D = 444 +INTR_X86_SSE2_PSRLI_Q = 445 +INTR_X86_SSE2_PSRLI_W = 446 +INTR_X86_SSE2_PSUBS_B = 447 +INTR_X86_SSE2_PSUBS_W = 448 +INTR_X86_SSE2_PSUBUS_B = 449 +INTR_X86_SSE2_PSUBUS_W = 450 +INTR_X86_SSE2_SQRT_PD = 451 +INTR_X86_SSE2_SQRT_SD = 452 +INTR_X86_SSE2_STOREL_DQ = 453 +INTR_X86_SSE2_STOREU_DQ = 454 +INTR_X86_SSE2_STOREU_PD = 455 +INTR_X86_SSE2_SUB_SD = 456 +INTR_X86_SSE2_UCOMIEQ_SD = 457 +INTR_X86_SSE2_UCOMIGE_SD = 458 +INTR_X86_SSE2_UCOMIGT_SD = 459 +INTR_X86_SSE2_UCOMILE_SD = 460 +INTR_X86_SSE2_UCOMILT_SD = 461 +INTR_X86_SSE2_UCOMINEQ_SD = 462 +INTR_X86_SSE3_ADDSUB_PD = 463 +INTR_X86_SSE3_ADDSUB_PS = 464 +INTR_X86_SSE3_HADD_PD = 465 +INTR_X86_SSE3_HADD_PS = 466 +INTR_X86_SSE3_HSUB_PD = 467 +INTR_X86_SSE3_HSUB_PS = 468 +INTR_X86_SSE3_LDU_DQ = 469 +INTR_X86_SSE3_MONITOR = 470 +INTR_X86_SSE3_MWAIT = 471 +INTR_X86_SSE41_BLENDPD = 472 +INTR_X86_SSE41_BLENDPS = 473 +INTR_X86_SSE41_BLENDVPD = 474 +INTR_X86_SSE41_BLENDVPS = 475 +INTR_X86_SSE41_DPPD = 476 +INTR_X86_SSE41_DPPS = 477 +INTR_X86_SSE41_EXTRACTPS = 478 +INTR_X86_SSE41_INSERTPS = 479 +INTR_X86_SSE41_MOVNTDQA = 480 +INTR_X86_SSE41_MPSADBW = 481 +INTR_X86_SSE41_PACKUSDW = 482 +INTR_X86_SSE41_PBLENDVB = 483 +INTR_X86_SSE41_PBLENDW = 484 +INTR_X86_SSE41_PCMPEQQ = 485 +INTR_X86_SSE41_PEXTRB = 486 +INTR_X86_SSE41_PEXTRD = 487 +INTR_X86_SSE41_PEXTRQ = 488 +INTR_X86_SSE41_PHMINPOSUW = 489 +INTR_X86_SSE41_PINSRB = 490 +INTR_X86_SSE41_PINSRD = 491 +INTR_X86_SSE41_PINSRQ = 492 +INTR_X86_SSE41_PMAXSB = 493 +INTR_X86_SSE41_PMAXSD = 494 +INTR_X86_SSE41_PMAXUD = 495 +INTR_X86_SSE41_PMAXUW = 496 +INTR_X86_SSE41_PMINSB = 497 +INTR_X86_SSE41_PMINSD = 498 +INTR_X86_SSE41_PMINUD = 499 +INTR_X86_SSE41_PMINUW = 500 +INTR_X86_SSE41_PMOVSXBD = 501 +INTR_X86_SSE41_PMOVSXBQ = 502 +INTR_X86_SSE41_PMOVSXBW = 503 +INTR_X86_SSE41_PMOVSXDQ = 504 +INTR_X86_SSE41_PMOVSXWD = 505 +INTR_X86_SSE41_PMOVSXWQ = 506 +INTR_X86_SSE41_PMOVZXBD = 507 +INTR_X86_SSE41_PMOVZXBQ = 508 +INTR_X86_SSE41_PMOVZXBW = 509 +INTR_X86_SSE41_PMOVZXDQ = 510 +INTR_X86_SSE41_PMOVZXWD = 511 +INTR_X86_SSE41_PMOVZXWQ = 512 +INTR_X86_SSE41_PMULDQ = 513 +INTR_X86_SSE41_PMULLD = 514 +INTR_X86_SSE41_ROUND_PD = 515 +INTR_X86_SSE41_ROUND_PS = 516 +INTR_X86_SSE41_ROUND_SD = 517 +INTR_X86_SSE41_ROUND_SS = 518 +INTR_X86_SSE42_PCMPGTQ = 519 +INTR_X86_SSE_ADD_SS = 520 +INTR_X86_SSE_CMP_PS = 521 +INTR_X86_SSE_CMP_SS = 522 +INTR_X86_SSE_COMIEQ_SS = 523 +INTR_X86_SSE_COMIGE_SS = 524 +INTR_X86_SSE_COMIGT_SS = 525 +INTR_X86_SSE_COMILE_SS = 526 +INTR_X86_SSE_COMILT_SS = 527 +INTR_X86_SSE_COMINEQ_SS = 528 +INTR_X86_SSE_CVTPD2PI = 529 +INTR_X86_SSE_CVTPI2PD = 530 +INTR_X86_SSE_CVTPI2PS = 531 +INTR_X86_SSE_CVTPS2PI = 532 +INTR_X86_SSE_CVTSI2SS = 533 +INTR_X86_SSE_CVTSI642SS = 534 +INTR_X86_SSE_CVTSS2SI = 535 +INTR_X86_SSE_CVTSS2SI64 = 536 +INTR_X86_SSE_CVTTPD2PI = 537 +INTR_X86_SSE_CVTTPS2PI = 538 +INTR_X86_SSE_CVTTSS2SI = 539 +INTR_X86_SSE_CVTTSS2SI64 = 540 +INTR_X86_SSE_DIV_SS = 541 +INTR_X86_SSE_LDMXCSR = 542 +INTR_X86_SSE_LOADU_PS = 543 +INTR_X86_SSE_MAX_PS = 544 +INTR_X86_SSE_MAX_SS = 545 +INTR_X86_SSE_MIN_PS = 546 +INTR_X86_SSE_MIN_SS = 547 +INTR_X86_SSE_MOVMSK_PS = 548 +INTR_X86_SSE_MOVNT_PS = 549 +INTR_X86_SSE_MUL_SS = 550 +INTR_X86_SSE_RCP_PS = 551 +INTR_X86_SSE_RCP_SS = 552 +INTR_X86_SSE_RSQRT_PS = 553 +INTR_X86_SSE_RSQRT_SS = 554 +INTR_X86_SSE_SFENCE = 555 +INTR_X86_SSE_SQRT_PS = 556 +INTR_X86_SSE_SQRT_SS = 557 +INTR_X86_SSE_STMXCSR = 558 +INTR_X86_SSE_STOREU_PS = 559 +INTR_X86_SSE_SUB_SS = 560 +INTR_X86_SSE_UCOMIEQ_SS = 561 +INTR_X86_SSE_UCOMIGE_SS = 562 +INTR_X86_SSE_UCOMIGT_SS = 563 +INTR_X86_SSE_UCOMILE_SS = 564 +INTR_X86_SSE_UCOMILT_SS = 565 +INTR_X86_SSE_UCOMINEQ_SS = 566 +INTR_X86_SSSE3_PABS_B = 567 +INTR_X86_SSSE3_PABS_B_128 = 568 +INTR_X86_SSSE3_PABS_D = 569 +INTR_X86_SSSE3_PABS_D_128 = 570 +INTR_X86_SSSE3_PABS_W = 571 +INTR_X86_SSSE3_PABS_W_128 = 572 +INTR_X86_SSSE3_PALIGN_R = 573 +INTR_X86_SSSE3_PALIGN_R_128 = 574 +INTR_X86_SSSE3_PHADD_D = 575 +INTR_X86_SSSE3_PHADD_D_128 = 576 +INTR_X86_SSSE3_PHADD_SW = 577 +INTR_X86_SSSE3_PHADD_SW_128 = 578 +INTR_X86_SSSE3_PHADD_W = 579 +INTR_X86_SSSE3_PHADD_W_128 = 580 +INTR_X86_SSSE3_PHSUB_D = 581 +INTR_X86_SSSE3_PHSUB_D_128 = 582 +INTR_X86_SSSE3_PHSUB_SW = 583 +INTR_X86_SSSE3_PHSUB_SW_128 = 584 +INTR_X86_SSSE3_PHSUB_W = 585 +INTR_X86_SSSE3_PHSUB_W_128 = 586 +INTR_X86_SSSE3_PMADD_UB_SW = 587 +INTR_X86_SSSE3_PMADD_UB_SW_128 = 588 +INTR_X86_SSSE3_PMUL_HR_SW = 589 +INTR_X86_SSSE3_PMUL_HR_SW_128 = 590 +INTR_X86_SSSE3_PSHUF_B = 591 +INTR_X86_SSSE3_PSHUF_B_128 = 592 +INTR_X86_SSSE3_PSIGN_B = 593 +INTR_X86_SSSE3_PSIGN_B_128 = 594 +INTR_X86_SSSE3_PSIGN_D = 595 +INTR_X86_SSSE3_PSIGN_D_128 = 596 +INTR_X86_SSSE3_PSIGN_W = 597 +INTR_X86_SSSE3_PSIGN_W_128 = 598 #===----------------------------------------------------------------------=== @@ -1654,10 +1658,10 @@ class Argument(Value): Value.__init__(self, ptr) def add_attribute(self, attr): - _core.LLVMAddParamAttr(self.ptr, attr) + _core.LLVMAddAttribute(self.ptr, attr) def remove_attribute(self, attr): - _core.LLVMRemoveParamAttr(self.ptr, attr) + _core.LLVMRemoveAttribute(self.ptr, attr) def set_alignment(self, align): _core.LLVMSetParamAlignment(self.ptr, align) @@ -1707,8 +1711,8 @@ class Function(GlobalValue): def _set_cc(self, value): _core.LLVMSetFunctionCallConv(self.ptr, value) calling_convention = property(_get_cc, _set_cc) - def _get_coll(self): return _core.LLVMGetCollector(self.ptr) - def _set_coll(self, value): _core.LLVMSetCollector(self.ptr, value) + def _get_coll(self): return _core.LLVMGetGC(self.ptr) + def _set_coll(self, value): _core.LLVMSetGC(self.ptr, value) collector = property(_get_coll, _set_coll) @property @@ -1813,10 +1817,10 @@ class CallOrInvokeInstruction(Instruction): calling_convention = property(_get_cc, _set_cc) def add_parameter_attribute(self, idx, attr): - _core.LLVMAddInstrParamAttr(self.ptr, idx, attr) + _core.LLVMAddInstrAttribute(self.ptr, idx, attr) def remove_parameter_attribute(self, idx, attr): - _core.LLVMRemoveInstrParamAttr(self.ptr, idx, attr) + _core.LLVMRemoveInstrAttribute(self.ptr, idx, attr) def set_parameter_alignment(self, idx, align): _core.LLVMSetInstrParamAlignment(self.ptr, idx, align) diff --git a/llvm/extra.cpp b/llvm/extra.cpp index 65058bf..cf47369 100644 --- a/llvm/extra.cpp +++ b/llvm/extra.cpp @@ -82,7 +82,11 @@ char *do_print(W obj) char *LLVMDumpModuleToString(LLVMModuleRef module) { - return do_print(module); + std::ostringstream buf; + llvm::Module *p = llvm::unwrap(module); + assert(p); + p->print(buf, NULL); + return strdup(buf.str().c_str()); } char *LLVMDumpTypeToString(LLVMTypeRef type) @@ -123,6 +127,14 @@ LLVMValueRef LLVMModuleGetOrInsertFunction(LLVMModuleRef module, return wrap(f); } +int LLVMHasInitializer(LLVMValueRef global_var) +{ + llvm::GlobalVariable *gvp = llvm::unwrap(global_var); + assert(gvp); + + return gvp->hasInitializer(); +} + #define inst_checkfn(ourfn, llvmfn) \ unsigned ourfn (LLVMValueRef v) { \ llvm::Instruction *ip = llvm::unwrap(v); \ @@ -191,10 +203,10 @@ LLVMValueRef LLVMBuildRetMultiple(LLVMBuilderRef builder, std::vector values_vec; unwrap_vec(values, n_values, values_vec); - llvm::IRBuilder *builderp = llvm::unwrap(builder); + llvm::IRBuilder<> *builderp = llvm::unwrap(builder); assert(builderp); - return wrap(builderp->CreateRet(&values_vec[0], values_vec.size())); + return llvm::wrap(builderp->CreateAggregateRet(&values_vec[0], values_vec.size())); } LLVMValueRef LLVMBuildGetResult(LLVMBuilderRef builder, @@ -202,10 +214,10 @@ LLVMValueRef LLVMBuildGetResult(LLVMBuilderRef builder, { assert(name); - llvm::IRBuilder *builderp = llvm::unwrap(builder); + llvm::IRBuilder<> *builderp = llvm::unwrap(builder); assert(builderp); - return wrap(builderp->CreateGetResult(llvm::unwrap(value), index, name)); + return llvm::wrap(builderp->CreateExtractValue(llvm::unwrap(value), index, name)); } LLVMValueRef LLVMGetIntrinsic(LLVMModuleRef module, int id, @@ -333,7 +345,7 @@ define_pass( DeadArgElimination ) define_pass( DeadTypeElimination ) define_pass( DeadInstElimination ) define_pass( DeadStoreElimination ) -define_pass( GCSE ) +/* define_pass( GCSE ): removed in LLVM 2.4 */ define_pass( GlobalDCE ) define_pass( GlobalOptimizer ) define_pass( GVNPRE ) diff --git a/llvm/extra.h b/llvm/extra.h index f592edd..0ff9333 100644 --- a/llvm/extra.h +++ b/llvm/extra.h @@ -77,6 +77,9 @@ unsigned LLVMModuleGetPointerSize(LLVMModuleRef module); LLVMValueRef LLVMModuleGetOrInsertFunction(LLVMModuleRef module, const char *name, LLVMTypeRef function_type); +/* Wraps llvm::GlobalVariable::hasInitializer(). */ +int LLVMHasInitializer(LLVMValueRef global_var); + /* The following functions wrap various llvm::Instruction::isXXX() functions. * All of them take an instruction and return 0 (isXXX returned false) or 1 * (isXXX returned false). */ @@ -143,7 +146,7 @@ declare_pass( DeadArgElimination ) declare_pass( DeadTypeElimination ) declare_pass( DeadInstElimination ) declare_pass( DeadStoreElimination ) -declare_pass( GCSE ) +/* declare_pass( GCSE ): removed in LLVM 2.4. */ declare_pass( GlobalDCE ) declare_pass( GlobalOptimizer ) declare_pass( GVNPRE ) diff --git a/llvm/passes.py b/llvm/passes.py index c9e99b5..5ffa11c 100644 --- a/llvm/passes.py +++ b/llvm/passes.py @@ -56,7 +56,7 @@ PASS_DEAD_ARG_ELIMINATION = 10 PASS_DEAD_TYPE_ELIMINATION = 11 PASS_DEAD_INST_ELIMINATION = 12 PASS_DEAD_STORE_ELIMINATION = 13 -PASS_GCSE = 14 +# PASS_GCSE = 14: removed in LLVM 2.4 PASS_GLOBAL_DCE = 15 PASS_GLOBAL_OPTIMIZER = 16 PASS_GVN = 17 @@ -127,7 +127,7 @@ _pass_creator = { PASS_DEAD_TYPE_ELIMINATION : _core.LLVMAddDeadTypeEliminationPass, PASS_DEAD_INST_ELIMINATION : _core.LLVMAddDeadInstEliminationPass, PASS_DEAD_STORE_ELIMINATION : _core.LLVMAddDeadStoreEliminationPass, - PASS_GCSE : _core.LLVMAddGCSEPass, + # PASS_GCSE : _core.LLVMAddGCSEPass,: removed in LLVM 2.4. PASS_GLOBAL_DCE : _core.LLVMAddGlobalDCEPass, PASS_GLOBAL_OPTIMIZER : _core.LLVMAddGlobalOptimizerPass, PASS_GVN : _core.LLVMAddGVNPass, diff --git a/setup.py b/setup.py index 92c308e..abd3f12 100644 --- a/setup.py +++ b/setup.py @@ -1,9 +1,38 @@ #!/usr/bin/env python +# +# Copyright (c) 2008, Mahadevan R All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of this software, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# import sys, os from distutils.core import setup, Extension -LLVM_PY_VERSION = '0.4' +LLVM_PY_VERSION = '0.5' def _run(cmd): diff --git a/test/testall.py b/test/testall.py index f13793e..1d1fc9f 100644 --- a/test/testall.py +++ b/test/testall.py @@ -351,6 +351,19 @@ def do_basicblock(): # ^ not working yet! +def _do_builder_mrv(): + m = Module.new('mrv') + ft = Type.function(Type.array(ti, 2), [ti]) + f = Function.new(m, ft, 'divrem') + blk = f.append_basic_block('b') + b = Builder.new(blk) + v = b.call(f, [Constant.int(ti, 1)]) + v1 = b.getresult(v, 0) + v2 = b.getresult(v, 1) + b.ret_many([v1, v2]) + #print f + + def do_builder(): print " Testing class Builder" m = Module.new('a') @@ -365,7 +378,8 @@ def do_builder(): blk2 = b.block b.ret_void() b.ret(Constant.int(ti, 10)) - b.ret_many([Constant.int(ti, 10)]*10) + _do_builder_mrv() + #b.ret_many([Constant.int(ti, 10)]*10) b.branch(blk) b.cbranch(Constant.int(Type.int(1), 1), blk, blk) b.switch(f.args[0], blk)