From d1bcdd05d1a2160b8d428a9ee78f8223f2e6734d Mon Sep 17 00:00:00 2001 From: Siu Kwan Lam Date: Sat, 18 Aug 2012 15:29:26 -0700 Subject: [PATCH] add NVPTX for LLVM 3.2; auto-gen _intrinsic_ids.py in setup.py; --- llvm/_core.cpp | 23 +- llvm/_intrinsic_ids.py | 1942 ---------------------------------------- llvm/core.py | 21 +- llvm/extra.cpp | 2 + llvm/extra.h | 13 +- setup.py | 37 +- test/targetmachines.py | 15 +- tools/__init__.py | 0 tools/intrgen.py | 7 +- 9 files changed, 99 insertions(+), 1961 deletions(-) delete mode 100644 llvm/_intrinsic_ids.py create mode 100644 tools/__init__.py diff --git a/llvm/_core.cpp b/llvm/_core.cpp index ae94e83..02eb8f8 100644 --- a/llvm/_core.cpp +++ b/llvm/_core.cpp @@ -43,6 +43,11 @@ #include "llvm-c/ExecutionEngine.h" #include "llvm-c/Target.h" #include "llvm-c/Transforms/IPO.h" +#if LLVM_VERSION_MAJOR >= 3 && LLVM_VERSION_MINOR >= 2 + #include "llvm-c/Linker.h" +#else + typedef unsigned int LLVMLinkerMode; +#endif /* libc includes */ #include /* for malloc(), free() */ @@ -225,7 +230,7 @@ _wLLVMLinkModules(PyObject *self, PyObject *args) dest = (LLVMModuleRef) PyCapsule_GetPointer(dest_obj, NULL); src = (LLVMModuleRef) PyCapsule_GetPointer(src_obj, NULL); - if (!LLVMLinkModules(dest, src, mode, &errmsg)) { + if (!LLVMLinkModules(dest, src, (LLVMLinkerMode)mode, &errmsg)) { if (errmsg) { ret = PyUnicode_FromString(errmsg); LLVMDisposeMessage(errmsg); @@ -897,11 +902,17 @@ _wrap_none2none(LLVMInitializePasses) _wrap_none2obj(LLVMInitializeNativeTarget, int) _wrap_none2obj(LLVMInitializeNativeTargetAsmPrinter, int) +#if LLVM_HAS_NVPTX +_wrap_none2none(LLVMInitializeNVPTXTarget) +_wrap_none2none(LLVMInitializeNVPTXTargetInfo) +_wrap_none2none( LLVMInitializeNVPTXTargetMC ) +_wrap_none2none(LLVMInitializeNVPTXAsmPrinter) +#else _wrap_none2none(LLVMInitializePTXTarget) _wrap_none2none(LLVMInitializePTXTargetInfo) _wrap_none2none( LLVMInitializePTXTargetMC ) _wrap_none2none(LLVMInitializePTXAsmPrinter) - +#endif /*===----------------------------------------------------------------------===*/ /* Passes */ @@ -1822,11 +1833,17 @@ static PyMethodDef core_methods[] = { _method( LLVMInitializeNativeTarget ) _method( LLVMInitializeNativeTargetAsmPrinter ) +#if LLVM_HAS_NVPTX + _method( LLVMInitializeNVPTXTarget ) + _method( LLVMInitializeNVPTXTargetInfo ) + _method( LLVMInitializeNVPTXTargetMC ) + _method( LLVMInitializeNVPTXAsmPrinter ) +#else _method( LLVMInitializePTXTarget ) _method( LLVMInitializePTXTargetInfo ) _method( LLVMInitializePTXTargetMC ) _method( LLVMInitializePTXAsmPrinter ) - +#endif /* Passes */ /* diff --git a/llvm/_intrinsic_ids.py b/llvm/_intrinsic_ids.py deleted file mode 100644 index c2e0ae5..0000000 --- a/llvm/_intrinsic_ids.py +++ /dev/null @@ -1,1942 +0,0 @@ -# -# Copyright (c) 2008-10, Mahadevan R All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of this software, nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -"""Intrinsic IDs. - -Intended to be imported into the llvm.core namespace. Not for public use.""" -# Generate these using the ../tools/intrgen.py file - -INTR_ADJUST_TRAMPOLINE = 1 -INTR_ANNOTATION = 2 -INTR_ARM_CDP = 3 -INTR_ARM_CDP2 = 4 -INTR_ARM_GET_FPSCR = 5 -INTR_ARM_LDREXD = 6 -INTR_ARM_MCR = 7 -INTR_ARM_MCR2 = 8 -INTR_ARM_MCRR = 9 -INTR_ARM_MCRR2 = 10 -INTR_ARM_MRC = 11 -INTR_ARM_MRC2 = 12 -INTR_ARM_NEON_VABDS = 13 -INTR_ARM_NEON_VABDU = 14 -INTR_ARM_NEON_VABS = 15 -INTR_ARM_NEON_VACGED = 16 -INTR_ARM_NEON_VACGEQ = 17 -INTR_ARM_NEON_VACGTD = 18 -INTR_ARM_NEON_VACGTQ = 19 -INTR_ARM_NEON_VADDHN = 20 -INTR_ARM_NEON_VCLS = 21 -INTR_ARM_NEON_VCLZ = 22 -INTR_ARM_NEON_VCNT = 23 -INTR_ARM_NEON_VCVTFP2FXS = 24 -INTR_ARM_NEON_VCVTFP2FXU = 25 -INTR_ARM_NEON_VCVTFP2HF = 26 -INTR_ARM_NEON_VCVTFXS2FP = 27 -INTR_ARM_NEON_VCVTFXU2FP = 28 -INTR_ARM_NEON_VCVTHF2FP = 29 -INTR_ARM_NEON_VHADDS = 30 -INTR_ARM_NEON_VHADDU = 31 -INTR_ARM_NEON_VHSUBS = 32 -INTR_ARM_NEON_VHSUBU = 33 -INTR_ARM_NEON_VLD1 = 34 -INTR_ARM_NEON_VLD2 = 35 -INTR_ARM_NEON_VLD2LANE = 36 -INTR_ARM_NEON_VLD3 = 37 -INTR_ARM_NEON_VLD3LANE = 38 -INTR_ARM_NEON_VLD4 = 39 -INTR_ARM_NEON_VLD4LANE = 40 -INTR_ARM_NEON_VMAXS = 41 -INTR_ARM_NEON_VMAXU = 42 -INTR_ARM_NEON_VMINS = 43 -INTR_ARM_NEON_VMINU = 44 -INTR_ARM_NEON_VMULLP = 45 -INTR_ARM_NEON_VMULLS = 46 -INTR_ARM_NEON_VMULLU = 47 -INTR_ARM_NEON_VMULP = 48 -INTR_ARM_NEON_VPADALS = 49 -INTR_ARM_NEON_VPADALU = 50 -INTR_ARM_NEON_VPADD = 51 -INTR_ARM_NEON_VPADDLS = 52 -INTR_ARM_NEON_VPADDLU = 53 -INTR_ARM_NEON_VPMAXS = 54 -INTR_ARM_NEON_VPMAXU = 55 -INTR_ARM_NEON_VPMINS = 56 -INTR_ARM_NEON_VPMINU = 57 -INTR_ARM_NEON_VQABS = 58 -INTR_ARM_NEON_VQADDS = 59 -INTR_ARM_NEON_VQADDU = 60 -INTR_ARM_NEON_VQDMLAL = 61 -INTR_ARM_NEON_VQDMLSL = 62 -INTR_ARM_NEON_VQDMULH = 63 -INTR_ARM_NEON_VQDMULL = 64 -INTR_ARM_NEON_VQMOVNS = 65 -INTR_ARM_NEON_VQMOVNSU = 66 -INTR_ARM_NEON_VQMOVNU = 67 -INTR_ARM_NEON_VQNEG = 68 -INTR_ARM_NEON_VQRDMULH = 69 -INTR_ARM_NEON_VQRSHIFTNS = 70 -INTR_ARM_NEON_VQRSHIFTNSU = 71 -INTR_ARM_NEON_VQRSHIFTNU = 72 -INTR_ARM_NEON_VQRSHIFTS = 73 -INTR_ARM_NEON_VQRSHIFTU = 74 -INTR_ARM_NEON_VQSHIFTNS = 75 -INTR_ARM_NEON_VQSHIFTNSU = 76 -INTR_ARM_NEON_VQSHIFTNU = 77 -INTR_ARM_NEON_VQSHIFTS = 78 -INTR_ARM_NEON_VQSHIFTSU = 79 -INTR_ARM_NEON_VQSHIFTU = 80 -INTR_ARM_NEON_VQSUBS = 81 -INTR_ARM_NEON_VQSUBU = 82 -INTR_ARM_NEON_VRADDHN = 83 -INTR_ARM_NEON_VRECPE = 84 -INTR_ARM_NEON_VRECPS = 85 -INTR_ARM_NEON_VRHADDS = 86 -INTR_ARM_NEON_VRHADDU = 87 -INTR_ARM_NEON_VRSHIFTN = 88 -INTR_ARM_NEON_VRSHIFTS = 89 -INTR_ARM_NEON_VRSHIFTU = 90 -INTR_ARM_NEON_VRSQRTE = 91 -INTR_ARM_NEON_VRSQRTS = 92 -INTR_ARM_NEON_VRSUBHN = 93 -INTR_ARM_NEON_VSHIFTINS = 94 -INTR_ARM_NEON_VSHIFTLS = 95 -INTR_ARM_NEON_VSHIFTLU = 96 -INTR_ARM_NEON_VSHIFTN = 97 -INTR_ARM_NEON_VSHIFTS = 98 -INTR_ARM_NEON_VSHIFTU = 99 -INTR_ARM_NEON_VST1 = 100 -INTR_ARM_NEON_VST2 = 101 -INTR_ARM_NEON_VST2LANE = 102 -INTR_ARM_NEON_VST3 = 103 -INTR_ARM_NEON_VST3LANE = 104 -INTR_ARM_NEON_VST4 = 105 -INTR_ARM_NEON_VST4LANE = 106 -INTR_ARM_NEON_VSUBHN = 107 -INTR_ARM_NEON_VTBL1 = 108 -INTR_ARM_NEON_VTBL2 = 109 -INTR_ARM_NEON_VTBL3 = 110 -INTR_ARM_NEON_VTBL4 = 111 -INTR_ARM_NEON_VTBX1 = 112 -INTR_ARM_NEON_VTBX2 = 113 -INTR_ARM_NEON_VTBX3 = 114 -INTR_ARM_NEON_VTBX4 = 115 -INTR_ARM_QADD = 116 -INTR_ARM_QSUB = 117 -INTR_ARM_SET_FPSCR = 118 -INTR_ARM_SSAT = 119 -INTR_ARM_STREXD = 120 -INTR_ARM_THREAD_POINTER = 121 -INTR_ARM_USAT = 122 -INTR_ARM_VCVTR = 123 -INTR_ARM_VCVTRU = 124 -INTR_BSWAP = 125 -INTR_CONVERT_FROM_FP16 = 126 -INTR_CONVERT_TO_FP16 = 127 -INTR_CONVERTFF = 128 -INTR_CONVERTFSI = 129 -INTR_CONVERTFUI = 130 -INTR_CONVERTSIF = 131 -INTR_CONVERTSS = 132 -INTR_CONVERTSU = 133 -INTR_CONVERTUIF = 134 -INTR_CONVERTUS = 135 -INTR_CONVERTUU = 136 -INTR_COS = 137 -INTR_CTLZ = 138 -INTR_CTPOP = 139 -INTR_CTTZ = 140 -INTR_DBG_DECLARE = 141 -INTR_DBG_VALUE = 142 -INTR_EH_DWARF_CFA = 143 -INTR_EH_RETURN_I32 = 144 -INTR_EH_RETURN_I64 = 145 -INTR_EH_SJLJ_CALLSITE = 146 -INTR_EH_SJLJ_FUNCTIONCONTEXT = 147 -INTR_EH_SJLJ_LONGJMP = 148 -INTR_EH_SJLJ_LSDA = 149 -INTR_EH_SJLJ_SETJMP = 150 -INTR_EH_TYPEID_FOR = 151 -INTR_EH_UNWIND_INIT = 152 -INTR_EXP = 153 -INTR_EXP2 = 154 -INTR_EXPECT = 155 -INTR_FLT_ROUNDS = 156 -INTR_FMA = 157 -INTR_FRAMEADDRESS = 158 -INTR_GCREAD = 159 -INTR_GCROOT = 160 -INTR_GCWRITE = 161 -INTR_HEXAGON_A2_ABS = 162 -INTR_HEXAGON_A2_ABSP = 163 -INTR_HEXAGON_A2_ABSSAT = 164 -INTR_HEXAGON_A2_ADD = 165 -INTR_HEXAGON_A2_ADDH_H16_HH = 166 -INTR_HEXAGON_A2_ADDH_H16_HL = 167 -INTR_HEXAGON_A2_ADDH_H16_LH = 168 -INTR_HEXAGON_A2_ADDH_H16_LL = 169 -INTR_HEXAGON_A2_ADDH_H16_SAT_HH = 170 -INTR_HEXAGON_A2_ADDH_H16_SAT_HL = 171 -INTR_HEXAGON_A2_ADDH_H16_SAT_LH = 172 -INTR_HEXAGON_A2_ADDH_H16_SAT_LL = 173 -INTR_HEXAGON_A2_ADDH_L16_HH = 174 -INTR_HEXAGON_A2_ADDH_L16_HL = 175 -INTR_HEXAGON_A2_ADDH_L16_LH = 176 -INTR_HEXAGON_A2_ADDH_L16_LL = 177 -INTR_HEXAGON_A2_ADDH_L16_SAT_HH = 178 -INTR_HEXAGON_A2_ADDH_L16_SAT_HL = 179 -INTR_HEXAGON_A2_ADDH_L16_SAT_LH = 180 -INTR_HEXAGON_A2_ADDH_L16_SAT_LL = 181 -INTR_HEXAGON_A2_ADDI = 182 -INTR_HEXAGON_A2_ADDP = 183 -INTR_HEXAGON_A2_ADDPSAT = 184 -INTR_HEXAGON_A2_ADDSAT = 185 -INTR_HEXAGON_A2_ADDSP = 186 -INTR_HEXAGON_A2_AND = 187 -INTR_HEXAGON_A2_ANDIR = 188 -INTR_HEXAGON_A2_ANDP = 189 -INTR_HEXAGON_A2_ASLH = 190 -INTR_HEXAGON_A2_ASRH = 191 -INTR_HEXAGON_A2_COMBINE_HH = 192 -INTR_HEXAGON_A2_COMBINE_HL = 193 -INTR_HEXAGON_A2_COMBINE_LH = 194 -INTR_HEXAGON_A2_COMBINE_LL = 195 -INTR_HEXAGON_A2_COMBINEII = 196 -INTR_HEXAGON_A2_COMBINEW = 197 -INTR_HEXAGON_A2_MAX = 198 -INTR_HEXAGON_A2_MAXP = 199 -INTR_HEXAGON_A2_MAXU = 200 -INTR_HEXAGON_A2_MAXUP = 201 -INTR_HEXAGON_A2_MIN = 202 -INTR_HEXAGON_A2_MINP = 203 -INTR_HEXAGON_A2_MINU = 204 -INTR_HEXAGON_A2_MINUP = 205 -INTR_HEXAGON_A2_NEG = 206 -INTR_HEXAGON_A2_NEGP = 207 -INTR_HEXAGON_A2_NEGSAT = 208 -INTR_HEXAGON_A2_NOT = 209 -INTR_HEXAGON_A2_NOTP = 210 -INTR_HEXAGON_A2_OR = 211 -INTR_HEXAGON_A2_ORIR = 212 -INTR_HEXAGON_A2_ORP = 213 -INTR_HEXAGON_A2_SAT = 214 -INTR_HEXAGON_A2_SATB = 215 -INTR_HEXAGON_A2_SATH = 216 -INTR_HEXAGON_A2_SATUB = 217 -INTR_HEXAGON_A2_SATUH = 218 -INTR_HEXAGON_A2_SUB = 219 -INTR_HEXAGON_A2_SUBH_H16_HH = 220 -INTR_HEXAGON_A2_SUBH_H16_HL = 221 -INTR_HEXAGON_A2_SUBH_H16_LH = 222 -INTR_HEXAGON_A2_SUBH_H16_LL = 223 -INTR_HEXAGON_A2_SUBH_H16_SAT_HH = 224 -INTR_HEXAGON_A2_SUBH_H16_SAT_HL = 225 -INTR_HEXAGON_A2_SUBH_H16_SAT_LH = 226 -INTR_HEXAGON_A2_SUBH_H16_SAT_LL = 227 -INTR_HEXAGON_A2_SUBH_L16_HL = 228 -INTR_HEXAGON_A2_SUBH_L16_LL = 229 -INTR_HEXAGON_A2_SUBH_L16_SAT_HL = 230 -INTR_HEXAGON_A2_SUBH_L16_SAT_LL = 231 -INTR_HEXAGON_A2_SUBP = 232 -INTR_HEXAGON_A2_SUBRI = 233 -INTR_HEXAGON_A2_SUBSAT = 234 -INTR_HEXAGON_A2_SVADDH = 235 -INTR_HEXAGON_A2_SVADDHS = 236 -INTR_HEXAGON_A2_SVADDUHS = 237 -INTR_HEXAGON_A2_SVAVGH = 238 -INTR_HEXAGON_A2_SVAVGHS = 239 -INTR_HEXAGON_A2_SVNAVGH = 240 -INTR_HEXAGON_A2_SVSUBH = 241 -INTR_HEXAGON_A2_SVSUBHS = 242 -INTR_HEXAGON_A2_SVSUBUHS = 243 -INTR_HEXAGON_A2_SWIZ = 244 -INTR_HEXAGON_A2_SXTB = 245 -INTR_HEXAGON_A2_SXTH = 246 -INTR_HEXAGON_A2_SXTW = 247 -INTR_HEXAGON_A2_TFR = 248 -INTR_HEXAGON_A2_TFRIH = 249 -INTR_HEXAGON_A2_TFRIL = 250 -INTR_HEXAGON_A2_TFRP = 251 -INTR_HEXAGON_A2_TFRPI = 252 -INTR_HEXAGON_A2_TFRSI = 253 -INTR_HEXAGON_A2_VABSH = 254 -INTR_HEXAGON_A2_VABSHSAT = 255 -INTR_HEXAGON_A2_VABSW = 256 -INTR_HEXAGON_A2_VABSWSAT = 257 -INTR_HEXAGON_A2_VADDH = 258 -INTR_HEXAGON_A2_VADDHS = 259 -INTR_HEXAGON_A2_VADDUB = 260 -INTR_HEXAGON_A2_VADDUBS = 261 -INTR_HEXAGON_A2_VADDUHS = 262 -INTR_HEXAGON_A2_VADDW = 263 -INTR_HEXAGON_A2_VADDWS = 264 -INTR_HEXAGON_A2_VAVGH = 265 -INTR_HEXAGON_A2_VAVGHCR = 266 -INTR_HEXAGON_A2_VAVGHR = 267 -INTR_HEXAGON_A2_VAVGUB = 268 -INTR_HEXAGON_A2_VAVGUBR = 269 -INTR_HEXAGON_A2_VAVGUH = 270 -INTR_HEXAGON_A2_VAVGUHR = 271 -INTR_HEXAGON_A2_VAVGUW = 272 -INTR_HEXAGON_A2_VAVGUWR = 273 -INTR_HEXAGON_A2_VAVGW = 274 -INTR_HEXAGON_A2_VAVGWCR = 275 -INTR_HEXAGON_A2_VAVGWR = 276 -INTR_HEXAGON_A2_VCMPBEQ = 277 -INTR_HEXAGON_A2_VCMPBGTU = 278 -INTR_HEXAGON_A2_VCMPHEQ = 279 -INTR_HEXAGON_A2_VCMPHGT = 280 -INTR_HEXAGON_A2_VCMPHGTU = 281 -INTR_HEXAGON_A2_VCMPWEQ = 282 -INTR_HEXAGON_A2_VCMPWGT = 283 -INTR_HEXAGON_A2_VCMPWGTU = 284 -INTR_HEXAGON_A2_VCONJ = 285 -INTR_HEXAGON_A2_VMAXH = 286 -INTR_HEXAGON_A2_VMAXUB = 287 -INTR_HEXAGON_A2_VMAXUH = 288 -INTR_HEXAGON_A2_VMAXUW = 289 -INTR_HEXAGON_A2_VMAXW = 290 -INTR_HEXAGON_A2_VMINH = 291 -INTR_HEXAGON_A2_VMINUB = 292 -INTR_HEXAGON_A2_VMINUH = 293 -INTR_HEXAGON_A2_VMINUW = 294 -INTR_HEXAGON_A2_VMINW = 295 -INTR_HEXAGON_A2_VNAVGH = 296 -INTR_HEXAGON_A2_VNAVGHCR = 297 -INTR_HEXAGON_A2_VNAVGHR = 298 -INTR_HEXAGON_A2_VNAVGW = 299 -INTR_HEXAGON_A2_VNAVGWCR = 300 -INTR_HEXAGON_A2_VNAVGWR = 301 -INTR_HEXAGON_A2_VRADDUB = 302 -INTR_HEXAGON_A2_VRADDUB_ACC = 303 -INTR_HEXAGON_A2_VRSADUB = 304 -INTR_HEXAGON_A2_VRSADUB_ACC = 305 -INTR_HEXAGON_A2_VSUBH = 306 -INTR_HEXAGON_A2_VSUBHS = 307 -INTR_HEXAGON_A2_VSUBUB = 308 -INTR_HEXAGON_A2_VSUBUBS = 309 -INTR_HEXAGON_A2_VSUBUHS = 310 -INTR_HEXAGON_A2_VSUBW = 311 -INTR_HEXAGON_A2_VSUBWS = 312 -INTR_HEXAGON_A2_XOR = 313 -INTR_HEXAGON_A2_XORP = 314 -INTR_HEXAGON_A2_ZXTB = 315 -INTR_HEXAGON_A2_ZXTH = 316 -INTR_HEXAGON_A4_ANDN = 317 -INTR_HEXAGON_A4_ANDNP = 318 -INTR_HEXAGON_A4_COMBINEIR = 319 -INTR_HEXAGON_A4_COMBINERI = 320 -INTR_HEXAGON_A4_CROUND_RI = 321 -INTR_HEXAGON_A4_CROUND_RR = 322 -INTR_HEXAGON_A4_MODWRAPU = 323 -INTR_HEXAGON_A4_ORN = 324 -INTR_HEXAGON_A4_ORNP = 325 -INTR_HEXAGON_A4_RCMPEQ = 326 -INTR_HEXAGON_A4_RCMPEQI = 327 -INTR_HEXAGON_A4_RCMPNEQ = 328 -INTR_HEXAGON_A4_RCMPNEQI = 329 -INTR_HEXAGON_A4_ROUND_RI = 330 -INTR_HEXAGON_A4_ROUND_RI_SAT = 331 -INTR_HEXAGON_A4_ROUND_RR = 332 -INTR_HEXAGON_A4_ROUND_RR_SAT = 333 -INTR_HEXAGON_C2_ALL8 = 334 -INTR_HEXAGON_C2_AND = 335 -INTR_HEXAGON_C2_ANDN = 336 -INTR_HEXAGON_C2_ANY8 = 337 -INTR_HEXAGON_C2_BITSCLR = 338 -INTR_HEXAGON_C2_BITSCLRI = 339 -INTR_HEXAGON_C2_BITSSET = 340 -INTR_HEXAGON_C2_CMPEQ = 341 -INTR_HEXAGON_C2_CMPEQI = 342 -INTR_HEXAGON_C2_CMPEQP = 343 -INTR_HEXAGON_C2_CMPGEI = 344 -INTR_HEXAGON_C2_CMPGEUI = 345 -INTR_HEXAGON_C2_CMPGT = 346 -INTR_HEXAGON_C2_CMPGTI = 347 -INTR_HEXAGON_C2_CMPGTP = 348 -INTR_HEXAGON_C2_CMPGTU = 349 -INTR_HEXAGON_C2_CMPGTUI = 350 -INTR_HEXAGON_C2_CMPGTUP = 351 -INTR_HEXAGON_C2_CMPLT = 352 -INTR_HEXAGON_C2_CMPLTU = 353 -INTR_HEXAGON_C2_MASK = 354 -INTR_HEXAGON_C2_MUX = 355 -INTR_HEXAGON_C2_MUXII = 356 -INTR_HEXAGON_C2_MUXIR = 357 -INTR_HEXAGON_C2_MUXRI = 358 -INTR_HEXAGON_C2_NOT = 359 -INTR_HEXAGON_C2_OR = 360 -INTR_HEXAGON_C2_ORN = 361 -INTR_HEXAGON_C2_PXFER_MAP = 362 -INTR_HEXAGON_C2_TFRPR = 363 -INTR_HEXAGON_C2_TFRRP = 364 -INTR_HEXAGON_C2_VITPACK = 365 -INTR_HEXAGON_C2_VMUX = 366 -INTR_HEXAGON_C2_XOR = 367 -INTR_HEXAGON_C4_AND_AND = 368 -INTR_HEXAGON_C4_AND_ANDN = 369 -INTR_HEXAGON_C4_AND_OR = 370 -INTR_HEXAGON_C4_AND_ORN = 371 -INTR_HEXAGON_C4_CMPLTE = 372 -INTR_HEXAGON_C4_CMPLTEI = 373 -INTR_HEXAGON_C4_CMPLTEU = 374 -INTR_HEXAGON_C4_CMPLTEUI = 375 -INTR_HEXAGON_C4_CMPNEQ = 376 -INTR_HEXAGON_C4_CMPNEQI = 377 -INTR_HEXAGON_C4_FASTCORNER9 = 378 -INTR_HEXAGON_C4_FASTCORNER9_NOT = 379 -INTR_HEXAGON_C4_OR_AND = 380 -INTR_HEXAGON_C4_OR_ANDN = 381 -INTR_HEXAGON_C4_OR_OR = 382 -INTR_HEXAGON_C4_OR_ORN = 383 -INTR_HEXAGON_M2_ACCI = 384 -INTR_HEXAGON_M2_ACCII = 385 -INTR_HEXAGON_M2_CMACI_S0 = 386 -INTR_HEXAGON_M2_CMACR_S0 = 387 -INTR_HEXAGON_M2_CMACS_S0 = 388 -INTR_HEXAGON_M2_CMACS_S1 = 389 -INTR_HEXAGON_M2_CMACSC_S0 = 390 -INTR_HEXAGON_M2_CMACSC_S1 = 391 -INTR_HEXAGON_M2_CMPYI_S0 = 392 -INTR_HEXAGON_M2_CMPYR_S0 = 393 -INTR_HEXAGON_M2_CMPYRS_S0 = 394 -INTR_HEXAGON_M2_CMPYRS_S1 = 395 -INTR_HEXAGON_M2_CMPYRSC_S0 = 396 -INTR_HEXAGON_M2_CMPYRSC_S1 = 397 -INTR_HEXAGON_M2_CMPYS_S0 = 398 -INTR_HEXAGON_M2_CMPYS_S1 = 399 -INTR_HEXAGON_M2_CMPYSC_S0 = 400 -INTR_HEXAGON_M2_CMPYSC_S1 = 401 -INTR_HEXAGON_M2_CNACS_S0 = 402 -INTR_HEXAGON_M2_CNACS_S1 = 403 -INTR_HEXAGON_M2_CNACSC_S0 = 404 -INTR_HEXAGON_M2_CNACSC_S1 = 405 -INTR_HEXAGON_M2_DPMPYSS_ACC_S0 = 406 -INTR_HEXAGON_M2_DPMPYSS_NAC_S0 = 407 -INTR_HEXAGON_M2_DPMPYSS_RND_S0 = 408 -INTR_HEXAGON_M2_DPMPYSS_S0 = 409 -INTR_HEXAGON_M2_DPMPYUU_ACC_S0 = 410 -INTR_HEXAGON_M2_DPMPYUU_NAC_S0 = 411 -INTR_HEXAGON_M2_DPMPYUU_S0 = 412 -INTR_HEXAGON_M2_HMMPYH_RS1 = 413 -INTR_HEXAGON_M2_HMMPYL_RS1 = 414 -INTR_HEXAGON_M2_MACI = 415 -INTR_HEXAGON_M2_MACSIN = 416 -INTR_HEXAGON_M2_MACSIP = 417 -INTR_HEXAGON_M2_MMACHS_RS0 = 418 -INTR_HEXAGON_M2_MMACHS_RS1 = 419 -INTR_HEXAGON_M2_MMACHS_S0 = 420 -INTR_HEXAGON_M2_MMACHS_S1 = 421 -INTR_HEXAGON_M2_MMACLS_RS0 = 422 -INTR_HEXAGON_M2_MMACLS_RS1 = 423 -INTR_HEXAGON_M2_MMACLS_S0 = 424 -INTR_HEXAGON_M2_MMACLS_S1 = 425 -INTR_HEXAGON_M2_MMACUHS_RS0 = 426 -INTR_HEXAGON_M2_MMACUHS_RS1 = 427 -INTR_HEXAGON_M2_MMACUHS_S0 = 428 -INTR_HEXAGON_M2_MMACUHS_S1 = 429 -INTR_HEXAGON_M2_MMACULS_RS0 = 430 -INTR_HEXAGON_M2_MMACULS_RS1 = 431 -INTR_HEXAGON_M2_MMACULS_S0 = 432 -INTR_HEXAGON_M2_MMACULS_S1 = 433 -INTR_HEXAGON_M2_MMPYH_RS0 = 434 -INTR_HEXAGON_M2_MMPYH_RS1 = 435 -INTR_HEXAGON_M2_MMPYH_S0 = 436 -INTR_HEXAGON_M2_MMPYH_S1 = 437 -INTR_HEXAGON_M2_MMPYL_RS0 = 438 -INTR_HEXAGON_M2_MMPYL_RS1 = 439 -INTR_HEXAGON_M2_MMPYL_S0 = 440 -INTR_HEXAGON_M2_MMPYL_S1 = 441 -INTR_HEXAGON_M2_MMPYUH_RS0 = 442 -INTR_HEXAGON_M2_MMPYUH_RS1 = 443 -INTR_HEXAGON_M2_MMPYUH_S0 = 444 -INTR_HEXAGON_M2_MMPYUH_S1 = 445 -INTR_HEXAGON_M2_MMPYUL_RS0 = 446 -INTR_HEXAGON_M2_MMPYUL_RS1 = 447 -INTR_HEXAGON_M2_MMPYUL_S0 = 448 -INTR_HEXAGON_M2_MMPYUL_S1 = 449 -INTR_HEXAGON_M2_MPY_ACC_HH_S0 = 450 -INTR_HEXAGON_M2_MPY_ACC_HH_S1 = 451 -INTR_HEXAGON_M2_MPY_ACC_HL_S0 = 452 -INTR_HEXAGON_M2_MPY_ACC_HL_S1 = 453 -INTR_HEXAGON_M2_MPY_ACC_LH_S0 = 454 -INTR_HEXAGON_M2_MPY_ACC_LH_S1 = 455 -INTR_HEXAGON_M2_MPY_ACC_LL_S0 = 456 -INTR_HEXAGON_M2_MPY_ACC_LL_S1 = 457 -INTR_HEXAGON_M2_MPY_ACC_SAT_HH_S0 = 458 -INTR_HEXAGON_M2_MPY_ACC_SAT_HH_S1 = 459 -INTR_HEXAGON_M2_MPY_ACC_SAT_HL_S0 = 460 -INTR_HEXAGON_M2_MPY_ACC_SAT_HL_S1 = 461 -INTR_HEXAGON_M2_MPY_ACC_SAT_LH_S0 = 462 -INTR_HEXAGON_M2_MPY_ACC_SAT_LH_S1 = 463 -INTR_HEXAGON_M2_MPY_ACC_SAT_LL_S0 = 464 -INTR_HEXAGON_M2_MPY_ACC_SAT_LL_S1 = 465 -INTR_HEXAGON_M2_MPY_HH_S0 = 466 -INTR_HEXAGON_M2_MPY_HH_S1 = 467 -INTR_HEXAGON_M2_MPY_HL_S0 = 468 -INTR_HEXAGON_M2_MPY_HL_S1 = 469 -INTR_HEXAGON_M2_MPY_LH_S0 = 470 -INTR_HEXAGON_M2_MPY_LH_S1 = 471 -INTR_HEXAGON_M2_MPY_LL_S0 = 472 -INTR_HEXAGON_M2_MPY_LL_S1 = 473 -INTR_HEXAGON_M2_MPY_NAC_HH_S0 = 474 -INTR_HEXAGON_M2_MPY_NAC_HH_S1 = 475 -INTR_HEXAGON_M2_MPY_NAC_HL_S0 = 476 -INTR_HEXAGON_M2_MPY_NAC_HL_S1 = 477 -INTR_HEXAGON_M2_MPY_NAC_LH_S0 = 478 -INTR_HEXAGON_M2_MPY_NAC_LH_S1 = 479 -INTR_HEXAGON_M2_MPY_NAC_LL_S0 = 480 -INTR_HEXAGON_M2_MPY_NAC_LL_S1 = 481 -INTR_HEXAGON_M2_MPY_NAC_SAT_HH_S0 = 482 -INTR_HEXAGON_M2_MPY_NAC_SAT_HH_S1 = 483 -INTR_HEXAGON_M2_MPY_NAC_SAT_HL_S0 = 484 -INTR_HEXAGON_M2_MPY_NAC_SAT_HL_S1 = 485 -INTR_HEXAGON_M2_MPY_NAC_SAT_LH_S0 = 486 -INTR_HEXAGON_M2_MPY_NAC_SAT_LH_S1 = 487 -INTR_HEXAGON_M2_MPY_NAC_SAT_LL_S0 = 488 -INTR_HEXAGON_M2_MPY_NAC_SAT_LL_S1 = 489 -INTR_HEXAGON_M2_MPY_RND_HH_S0 = 490 -INTR_HEXAGON_M2_MPY_RND_HH_S1 = 491 -INTR_HEXAGON_M2_MPY_RND_HL_S0 = 492 -INTR_HEXAGON_M2_MPY_RND_HL_S1 = 493 -INTR_HEXAGON_M2_MPY_RND_LH_S0 = 494 -INTR_HEXAGON_M2_MPY_RND_LH_S1 = 495 -INTR_HEXAGON_M2_MPY_RND_LL_S0 = 496 -INTR_HEXAGON_M2_MPY_RND_LL_S1 = 497 -INTR_HEXAGON_M2_MPY_SAT_HH_S0 = 498 -INTR_HEXAGON_M2_MPY_SAT_HH_S1 = 499 -INTR_HEXAGON_M2_MPY_SAT_HL_S0 = 500 -INTR_HEXAGON_M2_MPY_SAT_HL_S1 = 501 -INTR_HEXAGON_M2_MPY_SAT_LH_S0 = 502 -INTR_HEXAGON_M2_MPY_SAT_LH_S1 = 503 -INTR_HEXAGON_M2_MPY_SAT_LL_S0 = 504 -INTR_HEXAGON_M2_MPY_SAT_LL_S1 = 505 -INTR_HEXAGON_M2_MPY_SAT_RND_HH_S0 = 506 -INTR_HEXAGON_M2_MPY_SAT_RND_HH_S1 = 507 -INTR_HEXAGON_M2_MPY_SAT_RND_HL_S0 = 508 -INTR_HEXAGON_M2_MPY_SAT_RND_HL_S1 = 509 -INTR_HEXAGON_M2_MPY_SAT_RND_LH_S0 = 510 -INTR_HEXAGON_M2_MPY_SAT_RND_LH_S1 = 511 -INTR_HEXAGON_M2_MPY_SAT_RND_LL_S0 = 512 -INTR_HEXAGON_M2_MPY_SAT_RND_LL_S1 = 513 -INTR_HEXAGON_M2_MPY_UP = 514 -INTR_HEXAGON_M2_MPYD_ACC_HH_S0 = 515 -INTR_HEXAGON_M2_MPYD_ACC_HH_S1 = 516 -INTR_HEXAGON_M2_MPYD_ACC_HL_S0 = 517 -INTR_HEXAGON_M2_MPYD_ACC_HL_S1 = 518 -INTR_HEXAGON_M2_MPYD_ACC_LH_S0 = 519 -INTR_HEXAGON_M2_MPYD_ACC_LH_S1 = 520 -INTR_HEXAGON_M2_MPYD_ACC_LL_S0 = 521 -INTR_HEXAGON_M2_MPYD_ACC_LL_S1 = 522 -INTR_HEXAGON_M2_MPYD_HH_S0 = 523 -INTR_HEXAGON_M2_MPYD_HH_S1 = 524 -INTR_HEXAGON_M2_MPYD_HL_S0 = 525 -INTR_HEXAGON_M2_MPYD_HL_S1 = 526 -INTR_HEXAGON_M2_MPYD_LH_S0 = 527 -INTR_HEXAGON_M2_MPYD_LH_S1 = 528 -INTR_HEXAGON_M2_MPYD_LL_S0 = 529 -INTR_HEXAGON_M2_MPYD_LL_S1 = 530 -INTR_HEXAGON_M2_MPYD_NAC_HH_S0 = 531 -INTR_HEXAGON_M2_MPYD_NAC_HH_S1 = 532 -INTR_HEXAGON_M2_MPYD_NAC_HL_S0 = 533 -INTR_HEXAGON_M2_MPYD_NAC_HL_S1 = 534 -INTR_HEXAGON_M2_MPYD_NAC_LH_S0 = 535 -INTR_HEXAGON_M2_MPYD_NAC_LH_S1 = 536 -INTR_HEXAGON_M2_MPYD_NAC_LL_S0 = 537 -INTR_HEXAGON_M2_MPYD_NAC_LL_S1 = 538 -INTR_HEXAGON_M2_MPYD_RND_HH_S0 = 539 -INTR_HEXAGON_M2_MPYD_RND_HH_S1 = 540 -INTR_HEXAGON_M2_MPYD_RND_HL_S0 = 541 -INTR_HEXAGON_M2_MPYD_RND_HL_S1 = 542 -INTR_HEXAGON_M2_MPYD_RND_LH_S0 = 543 -INTR_HEXAGON_M2_MPYD_RND_LH_S1 = 544 -INTR_HEXAGON_M2_MPYD_RND_LL_S0 = 545 -INTR_HEXAGON_M2_MPYD_RND_LL_S1 = 546 -INTR_HEXAGON_M2_MPYI = 547 -INTR_HEXAGON_M2_MPYSMI = 548 -INTR_HEXAGON_M2_MPYU_ACC_HH_S0 = 549 -INTR_HEXAGON_M2_MPYU_ACC_HH_S1 = 550 -INTR_HEXAGON_M2_MPYU_ACC_HL_S0 = 551 -INTR_HEXAGON_M2_MPYU_ACC_HL_S1 = 552 -INTR_HEXAGON_M2_MPYU_ACC_LH_S0 = 553 -INTR_HEXAGON_M2_MPYU_ACC_LH_S1 = 554 -INTR_HEXAGON_M2_MPYU_ACC_LL_S0 = 555 -INTR_HEXAGON_M2_MPYU_ACC_LL_S1 = 556 -INTR_HEXAGON_M2_MPYU_HH_S0 = 557 -INTR_HEXAGON_M2_MPYU_HH_S1 = 558 -INTR_HEXAGON_M2_MPYU_HL_S0 = 559 -INTR_HEXAGON_M2_MPYU_HL_S1 = 560 -INTR_HEXAGON_M2_MPYU_LH_S0 = 561 -INTR_HEXAGON_M2_MPYU_LH_S1 = 562 -INTR_HEXAGON_M2_MPYU_LL_S0 = 563 -INTR_HEXAGON_M2_MPYU_LL_S1 = 564 -INTR_HEXAGON_M2_MPYU_NAC_HH_S0 = 565 -INTR_HEXAGON_M2_MPYU_NAC_HH_S1 = 566 -INTR_HEXAGON_M2_MPYU_NAC_HL_S0 = 567 -INTR_HEXAGON_M2_MPYU_NAC_HL_S1 = 568 -INTR_HEXAGON_M2_MPYU_NAC_LH_S0 = 569 -INTR_HEXAGON_M2_MPYU_NAC_LH_S1 = 570 -INTR_HEXAGON_M2_MPYU_NAC_LL_S0 = 571 -INTR_HEXAGON_M2_MPYU_NAC_LL_S1 = 572 -INTR_HEXAGON_M2_MPYU_UP = 573 -INTR_HEXAGON_M2_MPYUD_ACC_HH_S0 = 574 -INTR_HEXAGON_M2_MPYUD_ACC_HH_S1 = 575 -INTR_HEXAGON_M2_MPYUD_ACC_HL_S0 = 576 -INTR_HEXAGON_M2_MPYUD_ACC_HL_S1 = 577 -INTR_HEXAGON_M2_MPYUD_ACC_LH_S0 = 578 -INTR_HEXAGON_M2_MPYUD_ACC_LH_S1 = 579 -INTR_HEXAGON_M2_MPYUD_ACC_LL_S0 = 580 -INTR_HEXAGON_M2_MPYUD_ACC_LL_S1 = 581 -INTR_HEXAGON_M2_MPYUD_HH_S0 = 582 -INTR_HEXAGON_M2_MPYUD_HH_S1 = 583 -INTR_HEXAGON_M2_MPYUD_HL_S0 = 584 -INTR_HEXAGON_M2_MPYUD_HL_S1 = 585 -INTR_HEXAGON_M2_MPYUD_LH_S0 = 586 -INTR_HEXAGON_M2_MPYUD_LH_S1 = 587 -INTR_HEXAGON_M2_MPYUD_LL_S0 = 588 -INTR_HEXAGON_M2_MPYUD_LL_S1 = 589 -INTR_HEXAGON_M2_MPYUD_NAC_HH_S0 = 590 -INTR_HEXAGON_M2_MPYUD_NAC_HH_S1 = 591 -INTR_HEXAGON_M2_MPYUD_NAC_HL_S0 = 592 -INTR_HEXAGON_M2_MPYUD_NAC_HL_S1 = 593 -INTR_HEXAGON_M2_MPYUD_NAC_LH_S0 = 594 -INTR_HEXAGON_M2_MPYUD_NAC_LH_S1 = 595 -INTR_HEXAGON_M2_MPYUD_NAC_LL_S0 = 596 -INTR_HEXAGON_M2_MPYUD_NAC_LL_S1 = 597 -INTR_HEXAGON_M2_MPYUI = 598 -INTR_HEXAGON_M2_NACCI = 599 -INTR_HEXAGON_M2_NACCII = 600 -INTR_HEXAGON_M2_SUBACC = 601 -INTR_HEXAGON_M2_VABSDIFFH = 602 -INTR_HEXAGON_M2_VABSDIFFW = 603 -INTR_HEXAGON_M2_VCMAC_S0_SAT_I = 604 -INTR_HEXAGON_M2_VCMAC_S0_SAT_R = 605 -INTR_HEXAGON_M2_VCMPY_S0_SAT_I = 606 -INTR_HEXAGON_M2_VCMPY_S0_SAT_R = 607 -INTR_HEXAGON_M2_VCMPY_S1_SAT_I = 608 -INTR_HEXAGON_M2_VCMPY_S1_SAT_R = 609 -INTR_HEXAGON_M2_VDMACS_S0 = 610 -INTR_HEXAGON_M2_VDMACS_S1 = 611 -INTR_HEXAGON_M2_VDMPYRS_S0 = 612 -INTR_HEXAGON_M2_VDMPYRS_S1 = 613 -INTR_HEXAGON_M2_VDMPYS_S0 = 614 -INTR_HEXAGON_M2_VDMPYS_S1 = 615 -INTR_HEXAGON_M2_VMAC2 = 616 -INTR_HEXAGON_M2_VMAC2ES = 617 -INTR_HEXAGON_M2_VMAC2ES_S0 = 618 -INTR_HEXAGON_M2_VMAC2ES_S1 = 619 -INTR_HEXAGON_M2_VMAC2S_S0 = 620 -INTR_HEXAGON_M2_VMAC2S_S1 = 621 -INTR_HEXAGON_M2_VMPY2ES_S0 = 622 -INTR_HEXAGON_M2_VMPY2ES_S1 = 623 -INTR_HEXAGON_M2_VMPY2S_S0 = 624 -INTR_HEXAGON_M2_VMPY2S_S0PACK = 625 -INTR_HEXAGON_M2_VMPY2S_S1 = 626 -INTR_HEXAGON_M2_VMPY2S_S1PACK = 627 -INTR_HEXAGON_M2_VRADDUH = 628 -INTR_HEXAGON_M2_VRCMACI_S0 = 629 -INTR_HEXAGON_M2_VRCMACI_S0C = 630 -INTR_HEXAGON_M2_VRCMACR_S0 = 631 -INTR_HEXAGON_M2_VRCMACR_S0C = 632 -INTR_HEXAGON_M2_VRCMPYI_S0 = 633 -INTR_HEXAGON_M2_VRCMPYI_S0C = 634 -INTR_HEXAGON_M2_VRCMPYR_S0 = 635 -INTR_HEXAGON_M2_VRCMPYR_S0C = 636 -INTR_HEXAGON_M2_VRCMPYS_ACC_S1 = 637 -INTR_HEXAGON_M2_VRCMPYS_S1 = 638 -INTR_HEXAGON_M2_VRCMPYS_S1RP = 639 -INTR_HEXAGON_M2_VRMAC_S0 = 640 -INTR_HEXAGON_M2_VRMPY_S0 = 641 -INTR_HEXAGON_M2_XOR_XACC = 642 -INTR_HEXAGON_M4_AND_AND = 643 -INTR_HEXAGON_M4_AND_ANDN = 644 -INTR_HEXAGON_M4_AND_OR = 645 -INTR_HEXAGON_M4_AND_XOR = 646 -INTR_HEXAGON_M4_OR_AND = 647 -INTR_HEXAGON_M4_OR_ANDN = 648 -INTR_HEXAGON_M4_OR_OR = 649 -INTR_HEXAGON_M4_OR_XOR = 650 -INTR_HEXAGON_M4_XOR_AND = 651 -INTR_HEXAGON_M4_XOR_ANDN = 652 -INTR_HEXAGON_M4_XOR_OR = 653 -INTR_HEXAGON_M4_XOR_XACC = 654 -INTR_HEXAGON_S2_ADDASL_RRRI = 655 -INTR_HEXAGON_S2_ASL_I_P = 656 -INTR_HEXAGON_S2_ASL_I_P_ACC = 657 -INTR_HEXAGON_S2_ASL_I_P_AND = 658 -INTR_HEXAGON_S2_ASL_I_P_NAC = 659 -INTR_HEXAGON_S2_ASL_I_P_OR = 660 -INTR_HEXAGON_S2_ASL_I_P_XACC = 661 -INTR_HEXAGON_S2_ASL_I_R = 662 -INTR_HEXAGON_S2_ASL_I_R_ACC = 663 -INTR_HEXAGON_S2_ASL_I_R_AND = 664 -INTR_HEXAGON_S2_ASL_I_R_NAC = 665 -INTR_HEXAGON_S2_ASL_I_R_OR = 666 -INTR_HEXAGON_S2_ASL_I_R_SAT = 667 -INTR_HEXAGON_S2_ASL_I_R_XACC = 668 -INTR_HEXAGON_S2_ASL_I_VH = 669 -INTR_HEXAGON_S2_ASL_I_VW = 670 -INTR_HEXAGON_S2_ASL_R_P = 671 -INTR_HEXAGON_S2_ASL_R_P_ACC = 672 -INTR_HEXAGON_S2_ASL_R_P_AND = 673 -INTR_HEXAGON_S2_ASL_R_P_NAC = 674 -INTR_HEXAGON_S2_ASL_R_P_OR = 675 -INTR_HEXAGON_S2_ASL_R_R = 676 -INTR_HEXAGON_S2_ASL_R_R_ACC = 677 -INTR_HEXAGON_S2_ASL_R_R_AND = 678 -INTR_HEXAGON_S2_ASL_R_R_NAC = 679 -INTR_HEXAGON_S2_ASL_R_R_OR = 680 -INTR_HEXAGON_S2_ASL_R_R_SAT = 681 -INTR_HEXAGON_S2_ASL_R_VH = 682 -INTR_HEXAGON_S2_ASL_R_VW = 683 -INTR_HEXAGON_S2_ASR_I_P = 684 -INTR_HEXAGON_S2_ASR_I_P_ACC = 685 -INTR_HEXAGON_S2_ASR_I_P_AND = 686 -INTR_HEXAGON_S2_ASR_I_P_NAC = 687 -INTR_HEXAGON_S2_ASR_I_P_OR = 688 -INTR_HEXAGON_S2_ASR_I_R = 689 -INTR_HEXAGON_S2_ASR_I_R_ACC = 690 -INTR_HEXAGON_S2_ASR_I_R_AND = 691 -INTR_HEXAGON_S2_ASR_I_R_NAC = 692 -INTR_HEXAGON_S2_ASR_I_R_OR = 693 -INTR_HEXAGON_S2_ASR_I_R_RND = 694 -INTR_HEXAGON_S2_ASR_I_R_RND_GOODSYNTAX = 695 -INTR_HEXAGON_S2_ASR_I_SVW_TRUN = 696 -INTR_HEXAGON_S2_ASR_I_VH = 697 -INTR_HEXAGON_S2_ASR_I_VW = 698 -INTR_HEXAGON_S2_ASR_R_P = 699 -INTR_HEXAGON_S2_ASR_R_P_ACC = 700 -INTR_HEXAGON_S2_ASR_R_P_AND = 701 -INTR_HEXAGON_S2_ASR_R_P_NAC = 702 -INTR_HEXAGON_S2_ASR_R_P_OR = 703 -INTR_HEXAGON_S2_ASR_R_R = 704 -INTR_HEXAGON_S2_ASR_R_R_ACC = 705 -INTR_HEXAGON_S2_ASR_R_R_AND = 706 -INTR_HEXAGON_S2_ASR_R_R_NAC = 707 -INTR_HEXAGON_S2_ASR_R_R_OR = 708 -INTR_HEXAGON_S2_ASR_R_R_SAT = 709 -INTR_HEXAGON_S2_ASR_R_SVW_TRUN = 710 -INTR_HEXAGON_S2_ASR_R_VH = 711 -INTR_HEXAGON_S2_ASR_R_VW = 712 -INTR_HEXAGON_S2_BREV = 713 -INTR_HEXAGON_S2_CL0 = 714 -INTR_HEXAGON_S2_CL0P = 715 -INTR_HEXAGON_S2_CL1 = 716 -INTR_HEXAGON_S2_CL1P = 717 -INTR_HEXAGON_S2_CLB = 718 -INTR_HEXAGON_S2_CLBNORM = 719 -INTR_HEXAGON_S2_CLBP = 720 -INTR_HEXAGON_S2_CLRBIT_I = 721 -INTR_HEXAGON_S2_CLRBIT_R = 722 -INTR_HEXAGON_S2_CT0 = 723 -INTR_HEXAGON_S2_CT1 = 724 -INTR_HEXAGON_S2_DEINTERLEAVE = 725 -INTR_HEXAGON_S2_EXTRACTU = 726 -INTR_HEXAGON_S2_EXTRACTU_RP = 727 -INTR_HEXAGON_S2_EXTRACTUP = 728 -INTR_HEXAGON_S2_EXTRACTUP_RP = 729 -INTR_HEXAGON_S2_INSERT = 730 -INTR_HEXAGON_S2_INSERT_RP = 731 -INTR_HEXAGON_S2_INSERTP = 732 -INTR_HEXAGON_S2_INSERTP_RP = 733 -INTR_HEXAGON_S2_INTERLEAVE = 734 -INTR_HEXAGON_S2_LFSP = 735 -INTR_HEXAGON_S2_LSL_R_P = 736 -INTR_HEXAGON_S2_LSL_R_P_ACC = 737 -INTR_HEXAGON_S2_LSL_R_P_AND = 738 -INTR_HEXAGON_S2_LSL_R_P_NAC = 739 -INTR_HEXAGON_S2_LSL_R_P_OR = 740 -INTR_HEXAGON_S2_LSL_R_R = 741 -INTR_HEXAGON_S2_LSL_R_R_ACC = 742 -INTR_HEXAGON_S2_LSL_R_R_AND = 743 -INTR_HEXAGON_S2_LSL_R_R_NAC = 744 -INTR_HEXAGON_S2_LSL_R_R_OR = 745 -INTR_HEXAGON_S2_LSL_R_VH = 746 -INTR_HEXAGON_S2_LSL_R_VW = 747 -INTR_HEXAGON_S2_LSR_I_P = 748 -INTR_HEXAGON_S2_LSR_I_P_ACC = 749 -INTR_HEXAGON_S2_LSR_I_P_AND = 750 -INTR_HEXAGON_S2_LSR_I_P_NAC = 751 -INTR_HEXAGON_S2_LSR_I_P_OR = 752 -INTR_HEXAGON_S2_LSR_I_P_XACC = 753 -INTR_HEXAGON_S2_LSR_I_R = 754 -INTR_HEXAGON_S2_LSR_I_R_ACC = 755 -INTR_HEXAGON_S2_LSR_I_R_AND = 756 -INTR_HEXAGON_S2_LSR_I_R_NAC = 757 -INTR_HEXAGON_S2_LSR_I_R_OR = 758 -INTR_HEXAGON_S2_LSR_I_R_XACC = 759 -INTR_HEXAGON_S2_LSR_I_VH = 760 -INTR_HEXAGON_S2_LSR_I_VW = 761 -INTR_HEXAGON_S2_LSR_R_P = 762 -INTR_HEXAGON_S2_LSR_R_P_ACC = 763 -INTR_HEXAGON_S2_LSR_R_P_AND = 764 -INTR_HEXAGON_S2_LSR_R_P_NAC = 765 -INTR_HEXAGON_S2_LSR_R_P_OR = 766 -INTR_HEXAGON_S2_LSR_R_R = 767 -INTR_HEXAGON_S2_LSR_R_R_ACC = 768 -INTR_HEXAGON_S2_LSR_R_R_AND = 769 -INTR_HEXAGON_S2_LSR_R_R_NAC = 770 -INTR_HEXAGON_S2_LSR_R_R_OR = 771 -INTR_HEXAGON_S2_LSR_R_VH = 772 -INTR_HEXAGON_S2_LSR_R_VW = 773 -INTR_HEXAGON_S2_PACKHL = 774 -INTR_HEXAGON_S2_PARITYP = 775 -INTR_HEXAGON_S2_SETBIT_I = 776 -INTR_HEXAGON_S2_SETBIT_R = 777 -INTR_HEXAGON_S2_SHUFFEB = 778 -INTR_HEXAGON_S2_SHUFFEH = 779 -INTR_HEXAGON_S2_SHUFFOB = 780 -INTR_HEXAGON_S2_SHUFFOH = 781 -INTR_HEXAGON_S2_SVSATHB = 782 -INTR_HEXAGON_S2_SVSATHUB = 783 -INTR_HEXAGON_S2_TABLEIDXB_GOODSYNTAX = 784 -INTR_HEXAGON_S2_TABLEIDXD_GOODSYNTAX = 785 -INTR_HEXAGON_S2_TABLEIDXH_GOODSYNTAX = 786 -INTR_HEXAGON_S2_TABLEIDXW_GOODSYNTAX = 787 -INTR_HEXAGON_S2_TOGGLEBIT_I = 788 -INTR_HEXAGON_S2_TOGGLEBIT_R = 789 -INTR_HEXAGON_S2_TSTBIT_I = 790 -INTR_HEXAGON_S2_TSTBIT_R = 791 -INTR_HEXAGON_S2_VALIGNIB = 792 -INTR_HEXAGON_S2_VALIGNRB = 793 -INTR_HEXAGON_S2_VCROTATE = 794 -INTR_HEXAGON_S2_VRNDPACKWH = 795 -INTR_HEXAGON_S2_VRNDPACKWHS = 796 -INTR_HEXAGON_S2_VSATHB = 797 -INTR_HEXAGON_S2_VSATHB_NOPACK = 798 -INTR_HEXAGON_S2_VSATHUB = 799 -INTR_HEXAGON_S2_VSATHUB_NOPACK = 800 -INTR_HEXAGON_S2_VSATWH = 801 -INTR_HEXAGON_S2_VSATWH_NOPACK = 802 -INTR_HEXAGON_S2_VSATWUH = 803 -INTR_HEXAGON_S2_VSATWUH_NOPACK = 804 -INTR_HEXAGON_S2_VSPLATRB = 805 -INTR_HEXAGON_S2_VSPLATRH = 806 -INTR_HEXAGON_S2_VSPLICEIB = 807 -INTR_HEXAGON_S2_VSPLICERB = 808 -INTR_HEXAGON_S2_VSXTBH = 809 -INTR_HEXAGON_S2_VSXTHW = 810 -INTR_HEXAGON_S2_VTRUNEHB = 811 -INTR_HEXAGON_S2_VTRUNEWH = 812 -INTR_HEXAGON_S2_VTRUNOHB = 813 -INTR_HEXAGON_S2_VTRUNOWH = 814 -INTR_HEXAGON_S2_VZXTBH = 815 -INTR_HEXAGON_S2_VZXTHW = 816 -INTR_HEXAGON_S4_ADDADDI = 817 -INTR_HEXAGON_S4_ANDNP = 818 -INTR_HEXAGON_S4_OR_ANDI = 819 -INTR_HEXAGON_S4_OR_ANDIX = 820 -INTR_HEXAGON_S4_OR_ORI = 821 -INTR_HEXAGON_S4_ORNP = 822 -INTR_HEXAGON_S4_SUBADDI = 823 -INTR_HEXAGON_SI_TO_SXTHI_ASRH = 824 -INTR_INIT_TRAMPOLINE = 825 -INTR_INVARIANT_END = 826 -INTR_INVARIANT_START = 827 -INTR_LIFETIME_END = 828 -INTR_LIFETIME_START = 829 -INTR_LOG = 830 -INTR_LOG10 = 831 -INTR_LOG2 = 832 -INTR_LONGJMP = 833 -INTR_MEMCPY = 834 -INTR_MEMMOVE = 835 -INTR_MEMSET = 836 -INTR_OBJECTSIZE = 837 -INTR_PCMARKER = 838 -INTR_POW = 839 -INTR_POWI = 840 -INTR_PPC_ALTIVEC_DSS = 841 -INTR_PPC_ALTIVEC_DSSALL = 842 -INTR_PPC_ALTIVEC_DST = 843 -INTR_PPC_ALTIVEC_DSTST = 844 -INTR_PPC_ALTIVEC_DSTSTT = 845 -INTR_PPC_ALTIVEC_DSTT = 846 -INTR_PPC_ALTIVEC_LVEBX = 847 -INTR_PPC_ALTIVEC_LVEHX = 848 -INTR_PPC_ALTIVEC_LVEWX = 849 -INTR_PPC_ALTIVEC_LVSL = 850 -INTR_PPC_ALTIVEC_LVSR = 851 -INTR_PPC_ALTIVEC_LVX = 852 -INTR_PPC_ALTIVEC_LVXL = 853 -INTR_PPC_ALTIVEC_MFVSCR = 854 -INTR_PPC_ALTIVEC_MTVSCR = 855 -INTR_PPC_ALTIVEC_STVEBX = 856 -INTR_PPC_ALTIVEC_STVEHX = 857 -INTR_PPC_ALTIVEC_STVEWX = 858 -INTR_PPC_ALTIVEC_STVX = 859 -INTR_PPC_ALTIVEC_STVXL = 860 -INTR_PPC_ALTIVEC_VADDCUW = 861 -INTR_PPC_ALTIVEC_VADDSBS = 862 -INTR_PPC_ALTIVEC_VADDSHS = 863 -INTR_PPC_ALTIVEC_VADDSWS = 864 -INTR_PPC_ALTIVEC_VADDUBS = 865 -INTR_PPC_ALTIVEC_VADDUHS = 866 -INTR_PPC_ALTIVEC_VADDUWS = 867 -INTR_PPC_ALTIVEC_VAVGSB = 868 -INTR_PPC_ALTIVEC_VAVGSH = 869 -INTR_PPC_ALTIVEC_VAVGSW = 870 -INTR_PPC_ALTIVEC_VAVGUB = 871 -INTR_PPC_ALTIVEC_VAVGUH = 872 -INTR_PPC_ALTIVEC_VAVGUW = 873 -INTR_PPC_ALTIVEC_VCFSX = 874 -INTR_PPC_ALTIVEC_VCFUX = 875 -INTR_PPC_ALTIVEC_VCMPBFP = 876 -INTR_PPC_ALTIVEC_VCMPBFP_P = 877 -INTR_PPC_ALTIVEC_VCMPEQFP = 878 -INTR_PPC_ALTIVEC_VCMPEQFP_P = 879 -INTR_PPC_ALTIVEC_VCMPEQUB = 880 -INTR_PPC_ALTIVEC_VCMPEQUB_P = 881 -INTR_PPC_ALTIVEC_VCMPEQUH = 882 -INTR_PPC_ALTIVEC_VCMPEQUH_P = 883 -INTR_PPC_ALTIVEC_VCMPEQUW = 884 -INTR_PPC_ALTIVEC_VCMPEQUW_P = 885 -INTR_PPC_ALTIVEC_VCMPGEFP = 886 -INTR_PPC_ALTIVEC_VCMPGEFP_P = 887 -INTR_PPC_ALTIVEC_VCMPGTFP = 888 -INTR_PPC_ALTIVEC_VCMPGTFP_P = 889 -INTR_PPC_ALTIVEC_VCMPGTSB = 890 -INTR_PPC_ALTIVEC_VCMPGTSB_P = 891 -INTR_PPC_ALTIVEC_VCMPGTSH = 892 -INTR_PPC_ALTIVEC_VCMPGTSH_P = 893 -INTR_PPC_ALTIVEC_VCMPGTSW = 894 -INTR_PPC_ALTIVEC_VCMPGTSW_P = 895 -INTR_PPC_ALTIVEC_VCMPGTUB = 896 -INTR_PPC_ALTIVEC_VCMPGTUB_P = 897 -INTR_PPC_ALTIVEC_VCMPGTUH = 898 -INTR_PPC_ALTIVEC_VCMPGTUH_P = 899 -INTR_PPC_ALTIVEC_VCMPGTUW = 900 -INTR_PPC_ALTIVEC_VCMPGTUW_P = 901 -INTR_PPC_ALTIVEC_VCTSXS = 902 -INTR_PPC_ALTIVEC_VCTUXS = 903 -INTR_PPC_ALTIVEC_VEXPTEFP = 904 -INTR_PPC_ALTIVEC_VLOGEFP = 905 -INTR_PPC_ALTIVEC_VMADDFP = 906 -INTR_PPC_ALTIVEC_VMAXFP = 907 -INTR_PPC_ALTIVEC_VMAXSB = 908 -INTR_PPC_ALTIVEC_VMAXSH = 909 -INTR_PPC_ALTIVEC_VMAXSW = 910 -INTR_PPC_ALTIVEC_VMAXUB = 911 -INTR_PPC_ALTIVEC_VMAXUH = 912 -INTR_PPC_ALTIVEC_VMAXUW = 913 -INTR_PPC_ALTIVEC_VMHADDSHS = 914 -INTR_PPC_ALTIVEC_VMHRADDSHS = 915 -INTR_PPC_ALTIVEC_VMINFP = 916 -INTR_PPC_ALTIVEC_VMINSB = 917 -INTR_PPC_ALTIVEC_VMINSH = 918 -INTR_PPC_ALTIVEC_VMINSW = 919 -INTR_PPC_ALTIVEC_VMINUB = 920 -INTR_PPC_ALTIVEC_VMINUH = 921 -INTR_PPC_ALTIVEC_VMINUW = 922 -INTR_PPC_ALTIVEC_VMLADDUHM = 923 -INTR_PPC_ALTIVEC_VMSUMMBM = 924 -INTR_PPC_ALTIVEC_VMSUMSHM = 925 -INTR_PPC_ALTIVEC_VMSUMSHS = 926 -INTR_PPC_ALTIVEC_VMSUMUBM = 927 -INTR_PPC_ALTIVEC_VMSUMUHM = 928 -INTR_PPC_ALTIVEC_VMSUMUHS = 929 -INTR_PPC_ALTIVEC_VMULESB = 930 -INTR_PPC_ALTIVEC_VMULESH = 931 -INTR_PPC_ALTIVEC_VMULEUB = 932 -INTR_PPC_ALTIVEC_VMULEUH = 933 -INTR_PPC_ALTIVEC_VMULOSB = 934 -INTR_PPC_ALTIVEC_VMULOSH = 935 -INTR_PPC_ALTIVEC_VMULOUB = 936 -INTR_PPC_ALTIVEC_VMULOUH = 937 -INTR_PPC_ALTIVEC_VNMSUBFP = 938 -INTR_PPC_ALTIVEC_VPERM = 939 -INTR_PPC_ALTIVEC_VPKPX = 940 -INTR_PPC_ALTIVEC_VPKSHSS = 941 -INTR_PPC_ALTIVEC_VPKSHUS = 942 -INTR_PPC_ALTIVEC_VPKSWSS = 943 -INTR_PPC_ALTIVEC_VPKSWUS = 944 -INTR_PPC_ALTIVEC_VPKUHUS = 945 -INTR_PPC_ALTIVEC_VPKUWUS = 946 -INTR_PPC_ALTIVEC_VREFP = 947 -INTR_PPC_ALTIVEC_VRFIM = 948 -INTR_PPC_ALTIVEC_VRFIN = 949 -INTR_PPC_ALTIVEC_VRFIP = 950 -INTR_PPC_ALTIVEC_VRFIZ = 951 -INTR_PPC_ALTIVEC_VRLB = 952 -INTR_PPC_ALTIVEC_VRLH = 953 -INTR_PPC_ALTIVEC_VRLW = 954 -INTR_PPC_ALTIVEC_VRSQRTEFP = 955 -INTR_PPC_ALTIVEC_VSEL = 956 -INTR_PPC_ALTIVEC_VSL = 957 -INTR_PPC_ALTIVEC_VSLB = 958 -INTR_PPC_ALTIVEC_VSLH = 959 -INTR_PPC_ALTIVEC_VSLO = 960 -INTR_PPC_ALTIVEC_VSLW = 961 -INTR_PPC_ALTIVEC_VSR = 962 -INTR_PPC_ALTIVEC_VSRAB = 963 -INTR_PPC_ALTIVEC_VSRAH = 964 -INTR_PPC_ALTIVEC_VSRAW = 965 -INTR_PPC_ALTIVEC_VSRB = 966 -INTR_PPC_ALTIVEC_VSRH = 967 -INTR_PPC_ALTIVEC_VSRO = 968 -INTR_PPC_ALTIVEC_VSRW = 969 -INTR_PPC_ALTIVEC_VSUBCUW = 970 -INTR_PPC_ALTIVEC_VSUBSBS = 971 -INTR_PPC_ALTIVEC_VSUBSHS = 972 -INTR_PPC_ALTIVEC_VSUBSWS = 973 -INTR_PPC_ALTIVEC_VSUBUBS = 974 -INTR_PPC_ALTIVEC_VSUBUHS = 975 -INTR_PPC_ALTIVEC_VSUBUWS = 976 -INTR_PPC_ALTIVEC_VSUM2SWS = 977 -INTR_PPC_ALTIVEC_VSUM4SBS = 978 -INTR_PPC_ALTIVEC_VSUM4SHS = 979 -INTR_PPC_ALTIVEC_VSUM4UBS = 980 -INTR_PPC_ALTIVEC_VSUMSWS = 981 -INTR_PPC_ALTIVEC_VUPKHPX = 982 -INTR_PPC_ALTIVEC_VUPKHSB = 983 -INTR_PPC_ALTIVEC_VUPKHSH = 984 -INTR_PPC_ALTIVEC_VUPKLPX = 985 -INTR_PPC_ALTIVEC_VUPKLSB = 986 -INTR_PPC_ALTIVEC_VUPKLSH = 987 -INTR_PPC_DCBA = 988 -INTR_PPC_DCBF = 989 -INTR_PPC_DCBI = 990 -INTR_PPC_DCBST = 991 -INTR_PPC_DCBT = 992 -INTR_PPC_DCBTST = 993 -INTR_PPC_DCBZ = 994 -INTR_PPC_DCBZL = 995 -INTR_PPC_SYNC = 996 -INTR_PREFETCH = 997 -INTR_PTR_ANNOTATION = 998 -INTR_PTX_BAR_SYNC = 999 -INTR_PTX_READ_CLOCK = 1000 -INTR_PTX_READ_CLOCK64 = 1001 -INTR_PTX_READ_CTAID_W = 1002 -INTR_PTX_READ_CTAID_X = 1003 -INTR_PTX_READ_CTAID_Y = 1004 -INTR_PTX_READ_CTAID_Z = 1005 -INTR_PTX_READ_GRIDID = 1006 -INTR_PTX_READ_LANEID = 1007 -INTR_PTX_READ_LANEMASK_EQ = 1008 -INTR_PTX_READ_LANEMASK_GE = 1009 -INTR_PTX_READ_LANEMASK_GT = 1010 -INTR_PTX_READ_LANEMASK_LE = 1011 -INTR_PTX_READ_LANEMASK_LT = 1012 -INTR_PTX_READ_NCTAID_W = 1013 -INTR_PTX_READ_NCTAID_X = 1014 -INTR_PTX_READ_NCTAID_Y = 1015 -INTR_PTX_READ_NCTAID_Z = 1016 -INTR_PTX_READ_NSMID = 1017 -INTR_PTX_READ_NTID_W = 1018 -INTR_PTX_READ_NTID_X = 1019 -INTR_PTX_READ_NTID_Y = 1020 -INTR_PTX_READ_NTID_Z = 1021 -INTR_PTX_READ_NWARPID = 1022 -INTR_PTX_READ_PM0 = 1023 -INTR_PTX_READ_PM1 = 1024 -INTR_PTX_READ_PM2 = 1025 -INTR_PTX_READ_PM3 = 1026 -INTR_PTX_READ_SMID = 1027 -INTR_PTX_READ_TID_W = 1028 -INTR_PTX_READ_TID_X = 1029 -INTR_PTX_READ_TID_Y = 1030 -INTR_PTX_READ_TID_Z = 1031 -INTR_PTX_READ_WARPID = 1032 -INTR_READCYCLECOUNTER = 1033 -INTR_RETURNADDRESS = 1034 -INTR_SADD_WITH_OVERFLOW = 1035 -INTR_SETJMP = 1036 -INTR_SIGLONGJMP = 1037 -INTR_SIGSETJMP = 1038 -INTR_SIN = 1039 -INTR_SMUL_WITH_OVERFLOW = 1040 -INTR_SPU_SI_A = 1041 -INTR_SPU_SI_ADDX = 1042 -INTR_SPU_SI_AH = 1043 -INTR_SPU_SI_AHI = 1044 -INTR_SPU_SI_AI = 1045 -INTR_SPU_SI_AND = 1046 -INTR_SPU_SI_ANDBI = 1047 -INTR_SPU_SI_ANDC = 1048 -INTR_SPU_SI_ANDHI = 1049 -INTR_SPU_SI_ANDI = 1050 -INTR_SPU_SI_BG = 1051 -INTR_SPU_SI_BGX = 1052 -INTR_SPU_SI_CEQ = 1053 -INTR_SPU_SI_CEQB = 1054 -INTR_SPU_SI_CEQBI = 1055 -INTR_SPU_SI_CEQH = 1056 -INTR_SPU_SI_CEQHI = 1057 -INTR_SPU_SI_CEQI = 1058 -INTR_SPU_SI_CG = 1059 -INTR_SPU_SI_CGT = 1060 -INTR_SPU_SI_CGTB = 1061 -INTR_SPU_SI_CGTBI = 1062 -INTR_SPU_SI_CGTH = 1063 -INTR_SPU_SI_CGTHI = 1064 -INTR_SPU_SI_CGTI = 1065 -INTR_SPU_SI_CGX = 1066 -INTR_SPU_SI_CLGT = 1067 -INTR_SPU_SI_CLGTB = 1068 -INTR_SPU_SI_CLGTBI = 1069 -INTR_SPU_SI_CLGTH = 1070 -INTR_SPU_SI_CLGTHI = 1071 -INTR_SPU_SI_CLGTI = 1072 -INTR_SPU_SI_DFA = 1073 -INTR_SPU_SI_DFM = 1074 -INTR_SPU_SI_DFMA = 1075 -INTR_SPU_SI_DFMS = 1076 -INTR_SPU_SI_DFNMA = 1077 -INTR_SPU_SI_DFNMS = 1078 -INTR_SPU_SI_DFS = 1079 -INTR_SPU_SI_FA = 1080 -INTR_SPU_SI_FCEQ = 1081 -INTR_SPU_SI_FCGT = 1082 -INTR_SPU_SI_FCMEQ = 1083 -INTR_SPU_SI_FCMGT = 1084 -INTR_SPU_SI_FM = 1085 -INTR_SPU_SI_FMA = 1086 -INTR_SPU_SI_FMS = 1087 -INTR_SPU_SI_FNMS = 1088 -INTR_SPU_SI_FS = 1089 -INTR_SPU_SI_FSMBI = 1090 -INTR_SPU_SI_MPY = 1091 -INTR_SPU_SI_MPYA = 1092 -INTR_SPU_SI_MPYH = 1093 -INTR_SPU_SI_MPYHH = 1094 -INTR_SPU_SI_MPYHHA = 1095 -INTR_SPU_SI_MPYHHAU = 1096 -INTR_SPU_SI_MPYHHU = 1097 -INTR_SPU_SI_MPYI = 1098 -INTR_SPU_SI_MPYS = 1099 -INTR_SPU_SI_MPYU = 1100 -INTR_SPU_SI_MPYUI = 1101 -INTR_SPU_SI_NAND = 1102 -INTR_SPU_SI_NOR = 1103 -INTR_SPU_SI_OR = 1104 -INTR_SPU_SI_ORBI = 1105 -INTR_SPU_SI_ORC = 1106 -INTR_SPU_SI_ORHI = 1107 -INTR_SPU_SI_ORI = 1108 -INTR_SPU_SI_SF = 1109 -INTR_SPU_SI_SFH = 1110 -INTR_SPU_SI_SFHI = 1111 -INTR_SPU_SI_SFI = 1112 -INTR_SPU_SI_SFX = 1113 -INTR_SPU_SI_SHLI = 1114 -INTR_SPU_SI_SHLQBI = 1115 -INTR_SPU_SI_SHLQBII = 1116 -INTR_SPU_SI_SHLQBY = 1117 -INTR_SPU_SI_SHLQBYI = 1118 -INTR_SPU_SI_XOR = 1119 -INTR_SPU_SI_XORBI = 1120 -INTR_SPU_SI_XORHI = 1121 -INTR_SPU_SI_XORI = 1122 -INTR_SQRT = 1123 -INTR_SSUB_WITH_OVERFLOW = 1124 -INTR_STACKPROTECTOR = 1125 -INTR_STACKRESTORE = 1126 -INTR_STACKSAVE = 1127 -INTR_TRAP = 1128 -INTR_UADD_WITH_OVERFLOW = 1129 -INTR_UMUL_WITH_OVERFLOW = 1130 -INTR_USUB_WITH_OVERFLOW = 1131 -INTR_VACOPY = 1132 -INTR_VAEND = 1133 -INTR_VAR_ANNOTATION = 1134 -INTR_VASTART = 1135 -INTR_X86_3DNOW_PAVGUSB = 1136 -INTR_X86_3DNOW_PF2ID = 1137 -INTR_X86_3DNOW_PFACC = 1138 -INTR_X86_3DNOW_PFADD = 1139 -INTR_X86_3DNOW_PFCMPEQ = 1140 -INTR_X86_3DNOW_PFCMPGE = 1141 -INTR_X86_3DNOW_PFCMPGT = 1142 -INTR_X86_3DNOW_PFMAX = 1143 -INTR_X86_3DNOW_PFMIN = 1144 -INTR_X86_3DNOW_PFMUL = 1145 -INTR_X86_3DNOW_PFRCP = 1146 -INTR_X86_3DNOW_PFRCPIT1 = 1147 -INTR_X86_3DNOW_PFRCPIT2 = 1148 -INTR_X86_3DNOW_PFRSQIT1 = 1149 -INTR_X86_3DNOW_PFRSQRT = 1150 -INTR_X86_3DNOW_PFSUB = 1151 -INTR_X86_3DNOW_PFSUBR = 1152 -INTR_X86_3DNOW_PI2FD = 1153 -INTR_X86_3DNOW_PMULHRW = 1154 -INTR_X86_3DNOWA_PF2IW = 1155 -INTR_X86_3DNOWA_PFNACC = 1156 -INTR_X86_3DNOWA_PFPNACC = 1157 -INTR_X86_3DNOWA_PI2FW = 1158 -INTR_X86_3DNOWA_PSWAPD = 1159 -INTR_X86_AESNI_AESDEC = 1160 -INTR_X86_AESNI_AESDECLAST = 1161 -INTR_X86_AESNI_AESENC = 1162 -INTR_X86_AESNI_AESENCLAST = 1163 -INTR_X86_AESNI_AESIMC = 1164 -INTR_X86_AESNI_AESKEYGENASSIST = 1165 -INTR_X86_AVX2_MASKLOAD_D = 1166 -INTR_X86_AVX2_MASKLOAD_D_256 = 1167 -INTR_X86_AVX2_MASKLOAD_Q = 1168 -INTR_X86_AVX2_MASKLOAD_Q_256 = 1169 -INTR_X86_AVX2_MASKSTORE_D = 1170 -INTR_X86_AVX2_MASKSTORE_D_256 = 1171 -INTR_X86_AVX2_MASKSTORE_Q = 1172 -INTR_X86_AVX2_MASKSTORE_Q_256 = 1173 -INTR_X86_AVX2_MOVNTDQA = 1174 -INTR_X86_AVX2_MPSADBW = 1175 -INTR_X86_AVX2_PABS_B = 1176 -INTR_X86_AVX2_PABS_D = 1177 -INTR_X86_AVX2_PABS_W = 1178 -INTR_X86_AVX2_PACKSSDW = 1179 -INTR_X86_AVX2_PACKSSWB = 1180 -INTR_X86_AVX2_PACKUSDW = 1181 -INTR_X86_AVX2_PACKUSWB = 1182 -INTR_X86_AVX2_PADDS_B = 1183 -INTR_X86_AVX2_PADDS_W = 1184 -INTR_X86_AVX2_PADDUS_B = 1185 -INTR_X86_AVX2_PADDUS_W = 1186 -INTR_X86_AVX2_PAVG_B = 1187 -INTR_X86_AVX2_PAVG_W = 1188 -INTR_X86_AVX2_PBLENDD_128 = 1189 -INTR_X86_AVX2_PBLENDD_256 = 1190 -INTR_X86_AVX2_PBLENDVB = 1191 -INTR_X86_AVX2_PBLENDW = 1192 -INTR_X86_AVX2_PBROADCASTB_128 = 1193 -INTR_X86_AVX2_PBROADCASTB_256 = 1194 -INTR_X86_AVX2_PBROADCASTD_128 = 1195 -INTR_X86_AVX2_PBROADCASTD_256 = 1196 -INTR_X86_AVX2_PBROADCASTQ_128 = 1197 -INTR_X86_AVX2_PBROADCASTQ_256 = 1198 -INTR_X86_AVX2_PBROADCASTW_128 = 1199 -INTR_X86_AVX2_PBROADCASTW_256 = 1200 -INTR_X86_AVX2_PERMD = 1201 -INTR_X86_AVX2_PERMPD = 1202 -INTR_X86_AVX2_PERMPS = 1203 -INTR_X86_AVX2_PERMQ = 1204 -INTR_X86_AVX2_PHADD_D = 1205 -INTR_X86_AVX2_PHADD_SW = 1206 -INTR_X86_AVX2_PHADD_W = 1207 -INTR_X86_AVX2_PHSUB_D = 1208 -INTR_X86_AVX2_PHSUB_SW = 1209 -INTR_X86_AVX2_PHSUB_W = 1210 -INTR_X86_AVX2_PMADD_UB_SW = 1211 -INTR_X86_AVX2_PMADD_WD = 1212 -INTR_X86_AVX2_PMAXS_B = 1213 -INTR_X86_AVX2_PMAXS_D = 1214 -INTR_X86_AVX2_PMAXS_W = 1215 -INTR_X86_AVX2_PMAXU_B = 1216 -INTR_X86_AVX2_PMAXU_D = 1217 -INTR_X86_AVX2_PMAXU_W = 1218 -INTR_X86_AVX2_PMINS_B = 1219 -INTR_X86_AVX2_PMINS_D = 1220 -INTR_X86_AVX2_PMINS_W = 1221 -INTR_X86_AVX2_PMINU_B = 1222 -INTR_X86_AVX2_PMINU_D = 1223 -INTR_X86_AVX2_PMINU_W = 1224 -INTR_X86_AVX2_PMOVMSKB = 1225 -INTR_X86_AVX2_PMOVSXBD = 1226 -INTR_X86_AVX2_PMOVSXBQ = 1227 -INTR_X86_AVX2_PMOVSXBW = 1228 -INTR_X86_AVX2_PMOVSXDQ = 1229 -INTR_X86_AVX2_PMOVSXWD = 1230 -INTR_X86_AVX2_PMOVSXWQ = 1231 -INTR_X86_AVX2_PMOVZXBD = 1232 -INTR_X86_AVX2_PMOVZXBQ = 1233 -INTR_X86_AVX2_PMOVZXBW = 1234 -INTR_X86_AVX2_PMOVZXDQ = 1235 -INTR_X86_AVX2_PMOVZXWD = 1236 -INTR_X86_AVX2_PMOVZXWQ = 1237 -INTR_X86_AVX2_PMUL_DQ = 1238 -INTR_X86_AVX2_PMUL_HR_SW = 1239 -INTR_X86_AVX2_PMULH_W = 1240 -INTR_X86_AVX2_PMULHU_W = 1241 -INTR_X86_AVX2_PMULU_DQ = 1242 -INTR_X86_AVX2_PSAD_BW = 1243 -INTR_X86_AVX2_PSHUF_B = 1244 -INTR_X86_AVX2_PSIGN_B = 1245 -INTR_X86_AVX2_PSIGN_D = 1246 -INTR_X86_AVX2_PSIGN_W = 1247 -INTR_X86_AVX2_PSLL_D = 1248 -INTR_X86_AVX2_PSLL_DQ = 1249 -INTR_X86_AVX2_PSLL_DQ_BS = 1250 -INTR_X86_AVX2_PSLL_Q = 1251 -INTR_X86_AVX2_PSLL_W = 1252 -INTR_X86_AVX2_PSLLI_D = 1253 -INTR_X86_AVX2_PSLLI_Q = 1254 -INTR_X86_AVX2_PSLLI_W = 1255 -INTR_X86_AVX2_PSLLV_D = 1256 -INTR_X86_AVX2_PSLLV_D_256 = 1257 -INTR_X86_AVX2_PSLLV_Q = 1258 -INTR_X86_AVX2_PSLLV_Q_256 = 1259 -INTR_X86_AVX2_PSRA_D = 1260 -INTR_X86_AVX2_PSRA_W = 1261 -INTR_X86_AVX2_PSRAI_D = 1262 -INTR_X86_AVX2_PSRAI_W = 1263 -INTR_X86_AVX2_PSRAV_D = 1264 -INTR_X86_AVX2_PSRAV_D_256 = 1265 -INTR_X86_AVX2_PSRL_D = 1266 -INTR_X86_AVX2_PSRL_DQ = 1267 -INTR_X86_AVX2_PSRL_DQ_BS = 1268 -INTR_X86_AVX2_PSRL_Q = 1269 -INTR_X86_AVX2_PSRL_W = 1270 -INTR_X86_AVX2_PSRLI_D = 1271 -INTR_X86_AVX2_PSRLI_Q = 1272 -INTR_X86_AVX2_PSRLI_W = 1273 -INTR_X86_AVX2_PSRLV_D = 1274 -INTR_X86_AVX2_PSRLV_D_256 = 1275 -INTR_X86_AVX2_PSRLV_Q = 1276 -INTR_X86_AVX2_PSRLV_Q_256 = 1277 -INTR_X86_AVX2_PSUBS_B = 1278 -INTR_X86_AVX2_PSUBS_W = 1279 -INTR_X86_AVX2_PSUBUS_B = 1280 -INTR_X86_AVX2_PSUBUS_W = 1281 -INTR_X86_AVX2_VBROADCAST_SD_PD_256 = 1282 -INTR_X86_AVX2_VBROADCAST_SS_PS = 1283 -INTR_X86_AVX2_VBROADCAST_SS_PS_256 = 1284 -INTR_X86_AVX2_VBROADCASTI128 = 1285 -INTR_X86_AVX2_VEXTRACTI128 = 1286 -INTR_X86_AVX2_VINSERTI128 = 1287 -INTR_X86_AVX2_VPERM2I128 = 1288 -INTR_X86_AVX_ADDSUB_PD_256 = 1289 -INTR_X86_AVX_ADDSUB_PS_256 = 1290 -INTR_X86_AVX_BLEND_PD_256 = 1291 -INTR_X86_AVX_BLEND_PS_256 = 1292 -INTR_X86_AVX_BLENDV_PD_256 = 1293 -INTR_X86_AVX_BLENDV_PS_256 = 1294 -INTR_X86_AVX_CMP_PD_256 = 1295 -INTR_X86_AVX_CMP_PS_256 = 1296 -INTR_X86_AVX_CVT_PD2_PS_256 = 1297 -INTR_X86_AVX_CVT_PD2DQ_256 = 1298 -INTR_X86_AVX_CVT_PS2_PD_256 = 1299 -INTR_X86_AVX_CVT_PS2DQ_256 = 1300 -INTR_X86_AVX_CVTDQ2_PD_256 = 1301 -INTR_X86_AVX_CVTDQ2_PS_256 = 1302 -INTR_X86_AVX_CVTT_PD2DQ_256 = 1303 -INTR_X86_AVX_CVTT_PS2DQ_256 = 1304 -INTR_X86_AVX_DP_PS_256 = 1305 -INTR_X86_AVX_HADD_PD_256 = 1306 -INTR_X86_AVX_HADD_PS_256 = 1307 -INTR_X86_AVX_HSUB_PD_256 = 1308 -INTR_X86_AVX_HSUB_PS_256 = 1309 -INTR_X86_AVX_LDU_DQ_256 = 1310 -INTR_X86_AVX_MASKLOAD_PD = 1311 -INTR_X86_AVX_MASKLOAD_PD_256 = 1312 -INTR_X86_AVX_MASKLOAD_PS = 1313 -INTR_X86_AVX_MASKLOAD_PS_256 = 1314 -INTR_X86_AVX_MASKSTORE_PD = 1315 -INTR_X86_AVX_MASKSTORE_PD_256 = 1316 -INTR_X86_AVX_MASKSTORE_PS = 1317 -INTR_X86_AVX_MASKSTORE_PS_256 = 1318 -INTR_X86_AVX_MAX_PD_256 = 1319 -INTR_X86_AVX_MAX_PS_256 = 1320 -INTR_X86_AVX_MIN_PD_256 = 1321 -INTR_X86_AVX_MIN_PS_256 = 1322 -INTR_X86_AVX_MOVMSK_PD_256 = 1323 -INTR_X86_AVX_MOVMSK_PS_256 = 1324 -INTR_X86_AVX_MOVNT_DQ_256 = 1325 -INTR_X86_AVX_MOVNT_PD_256 = 1326 -INTR_X86_AVX_MOVNT_PS_256 = 1327 -INTR_X86_AVX_PTESTC_256 = 1328 -INTR_X86_AVX_PTESTNZC_256 = 1329 -INTR_X86_AVX_PTESTZ_256 = 1330 -INTR_X86_AVX_RCP_PS_256 = 1331 -INTR_X86_AVX_ROUND_PD_256 = 1332 -INTR_X86_AVX_ROUND_PS_256 = 1333 -INTR_X86_AVX_RSQRT_PS_256 = 1334 -INTR_X86_AVX_SQRT_PD_256 = 1335 -INTR_X86_AVX_SQRT_PS_256 = 1336 -INTR_X86_AVX_STOREU_DQ_256 = 1337 -INTR_X86_AVX_STOREU_PD_256 = 1338 -INTR_X86_AVX_STOREU_PS_256 = 1339 -INTR_X86_AVX_VBROADCAST_SD_256 = 1340 -INTR_X86_AVX_VBROADCAST_SS = 1341 -INTR_X86_AVX_VBROADCAST_SS_256 = 1342 -INTR_X86_AVX_VBROADCASTF128_PD_256 = 1343 -INTR_X86_AVX_VBROADCASTF128_PS_256 = 1344 -INTR_X86_AVX_VEXTRACTF128_PD_256 = 1345 -INTR_X86_AVX_VEXTRACTF128_PS_256 = 1346 -INTR_X86_AVX_VEXTRACTF128_SI_256 = 1347 -INTR_X86_AVX_VINSERTF128_PD_256 = 1348 -INTR_X86_AVX_VINSERTF128_PS_256 = 1349 -INTR_X86_AVX_VINSERTF128_SI_256 = 1350 -INTR_X86_AVX_VPERM2F128_PD_256 = 1351 -INTR_X86_AVX_VPERM2F128_PS_256 = 1352 -INTR_X86_AVX_VPERM2F128_SI_256 = 1353 -INTR_X86_AVX_VPERMIL_PD = 1354 -INTR_X86_AVX_VPERMIL_PD_256 = 1355 -INTR_X86_AVX_VPERMIL_PS = 1356 -INTR_X86_AVX_VPERMIL_PS_256 = 1357 -INTR_X86_AVX_VPERMILVAR_PD = 1358 -INTR_X86_AVX_VPERMILVAR_PD_256 = 1359 -INTR_X86_AVX_VPERMILVAR_PS = 1360 -INTR_X86_AVX_VPERMILVAR_PS_256 = 1361 -INTR_X86_AVX_VTESTC_PD = 1362 -INTR_X86_AVX_VTESTC_PD_256 = 1363 -INTR_X86_AVX_VTESTC_PS = 1364 -INTR_X86_AVX_VTESTC_PS_256 = 1365 -INTR_X86_AVX_VTESTNZC_PD = 1366 -INTR_X86_AVX_VTESTNZC_PD_256 = 1367 -INTR_X86_AVX_VTESTNZC_PS = 1368 -INTR_X86_AVX_VTESTNZC_PS_256 = 1369 -INTR_X86_AVX_VTESTZ_PD = 1370 -INTR_X86_AVX_VTESTZ_PD_256 = 1371 -INTR_X86_AVX_VTESTZ_PS = 1372 -INTR_X86_AVX_VTESTZ_PS_256 = 1373 -INTR_X86_AVX_VZEROALL = 1374 -INTR_X86_AVX_VZEROUPPER = 1375 -INTR_X86_BMI_BEXTR_32 = 1376 -INTR_X86_BMI_BEXTR_64 = 1377 -INTR_X86_BMI_BZHI_32 = 1378 -INTR_X86_BMI_BZHI_64 = 1379 -INTR_X86_BMI_PDEP_32 = 1380 -INTR_X86_BMI_PDEP_64 = 1381 -INTR_X86_BMI_PEXT_32 = 1382 -INTR_X86_BMI_PEXT_64 = 1383 -INTR_X86_FMA4_VFMADD_PD = 1384 -INTR_X86_FMA4_VFMADD_PD_256 = 1385 -INTR_X86_FMA4_VFMADD_PS = 1386 -INTR_X86_FMA4_VFMADD_PS_256 = 1387 -INTR_X86_FMA4_VFMADD_SD = 1388 -INTR_X86_FMA4_VFMADD_SS = 1389 -INTR_X86_FMA4_VFMADDSUB_PD = 1390 -INTR_X86_FMA4_VFMADDSUB_PD_256 = 1391 -INTR_X86_FMA4_VFMADDSUB_PS = 1392 -INTR_X86_FMA4_VFMADDSUB_PS_256 = 1393 -INTR_X86_FMA4_VFMSUB_PD = 1394 -INTR_X86_FMA4_VFMSUB_PD_256 = 1395 -INTR_X86_FMA4_VFMSUB_PS = 1396 -INTR_X86_FMA4_VFMSUB_PS_256 = 1397 -INTR_X86_FMA4_VFMSUB_SD = 1398 -INTR_X86_FMA4_VFMSUB_SS = 1399 -INTR_X86_FMA4_VFMSUBADD_PD = 1400 -INTR_X86_FMA4_VFMSUBADD_PD_256 = 1401 -INTR_X86_FMA4_VFMSUBADD_PS = 1402 -INTR_X86_FMA4_VFMSUBADD_PS_256 = 1403 -INTR_X86_FMA4_VFNMADD_PD = 1404 -INTR_X86_FMA4_VFNMADD_PD_256 = 1405 -INTR_X86_FMA4_VFNMADD_PS = 1406 -INTR_X86_FMA4_VFNMADD_PS_256 = 1407 -INTR_X86_FMA4_VFNMADD_SD = 1408 -INTR_X86_FMA4_VFNMADD_SS = 1409 -INTR_X86_FMA4_VFNMSUB_PD = 1410 -INTR_X86_FMA4_VFNMSUB_PD_256 = 1411 -INTR_X86_FMA4_VFNMSUB_PS = 1412 -INTR_X86_FMA4_VFNMSUB_PS_256 = 1413 -INTR_X86_FMA4_VFNMSUB_SD = 1414 -INTR_X86_FMA4_VFNMSUB_SS = 1415 -INTR_X86_INT = 1416 -INTR_X86_MMX_EMMS = 1417 -INTR_X86_MMX_FEMMS = 1418 -INTR_X86_MMX_MASKMOVQ = 1419 -INTR_X86_MMX_MOVNT_DQ = 1420 -INTR_X86_MMX_PACKSSDW = 1421 -INTR_X86_MMX_PACKSSWB = 1422 -INTR_X86_MMX_PACKUSWB = 1423 -INTR_X86_MMX_PADD_B = 1424 -INTR_X86_MMX_PADD_D = 1425 -INTR_X86_MMX_PADD_Q = 1426 -INTR_X86_MMX_PADD_W = 1427 -INTR_X86_MMX_PADDS_B = 1428 -INTR_X86_MMX_PADDS_W = 1429 -INTR_X86_MMX_PADDUS_B = 1430 -INTR_X86_MMX_PADDUS_W = 1431 -INTR_X86_MMX_PALIGNR_B = 1432 -INTR_X86_MMX_PAND = 1433 -INTR_X86_MMX_PANDN = 1434 -INTR_X86_MMX_PAVG_B = 1435 -INTR_X86_MMX_PAVG_W = 1436 -INTR_X86_MMX_PCMPEQ_B = 1437 -INTR_X86_MMX_PCMPEQ_D = 1438 -INTR_X86_MMX_PCMPEQ_W = 1439 -INTR_X86_MMX_PCMPGT_B = 1440 -INTR_X86_MMX_PCMPGT_D = 1441 -INTR_X86_MMX_PCMPGT_W = 1442 -INTR_X86_MMX_PEXTR_W = 1443 -INTR_X86_MMX_PINSR_W = 1444 -INTR_X86_MMX_PMADD_WD = 1445 -INTR_X86_MMX_PMAXS_W = 1446 -INTR_X86_MMX_PMAXU_B = 1447 -INTR_X86_MMX_PMINS_W = 1448 -INTR_X86_MMX_PMINU_B = 1449 -INTR_X86_MMX_PMOVMSKB = 1450 -INTR_X86_MMX_PMULH_W = 1451 -INTR_X86_MMX_PMULHU_W = 1452 -INTR_X86_MMX_PMULL_W = 1453 -INTR_X86_MMX_PMULU_DQ = 1454 -INTR_X86_MMX_POR = 1455 -INTR_X86_MMX_PSAD_BW = 1456 -INTR_X86_MMX_PSLL_D = 1457 -INTR_X86_MMX_PSLL_Q = 1458 -INTR_X86_MMX_PSLL_W = 1459 -INTR_X86_MMX_PSLLI_D = 1460 -INTR_X86_MMX_PSLLI_Q = 1461 -INTR_X86_MMX_PSLLI_W = 1462 -INTR_X86_MMX_PSRA_D = 1463 -INTR_X86_MMX_PSRA_W = 1464 -INTR_X86_MMX_PSRAI_D = 1465 -INTR_X86_MMX_PSRAI_W = 1466 -INTR_X86_MMX_PSRL_D = 1467 -INTR_X86_MMX_PSRL_Q = 1468 -INTR_X86_MMX_PSRL_W = 1469 -INTR_X86_MMX_PSRLI_D = 1470 -INTR_X86_MMX_PSRLI_Q = 1471 -INTR_X86_MMX_PSRLI_W = 1472 -INTR_X86_MMX_PSUB_B = 1473 -INTR_X86_MMX_PSUB_D = 1474 -INTR_X86_MMX_PSUB_Q = 1475 -INTR_X86_MMX_PSUB_W = 1476 -INTR_X86_MMX_PSUBS_B = 1477 -INTR_X86_MMX_PSUBS_W = 1478 -INTR_X86_MMX_PSUBUS_B = 1479 -INTR_X86_MMX_PSUBUS_W = 1480 -INTR_X86_MMX_PUNPCKHBW = 1481 -INTR_X86_MMX_PUNPCKHDQ = 1482 -INTR_X86_MMX_PUNPCKHWD = 1483 -INTR_X86_MMX_PUNPCKLBW = 1484 -INTR_X86_MMX_PUNPCKLDQ = 1485 -INTR_X86_MMX_PUNPCKLWD = 1486 -INTR_X86_MMX_PXOR = 1487 -INTR_X86_RDFSBASE_32 = 1488 -INTR_X86_RDFSBASE_64 = 1489 -INTR_X86_RDGSBASE_32 = 1490 -INTR_X86_RDGSBASE_64 = 1491 -INTR_X86_SSE2_ADD_SD = 1492 -INTR_X86_SSE2_CLFLUSH = 1493 -INTR_X86_SSE2_CMP_PD = 1494 -INTR_X86_SSE2_CMP_SD = 1495 -INTR_X86_SSE2_COMIEQ_SD = 1496 -INTR_X86_SSE2_COMIGE_SD = 1497 -INTR_X86_SSE2_COMIGT_SD = 1498 -INTR_X86_SSE2_COMILE_SD = 1499 -INTR_X86_SSE2_COMILT_SD = 1500 -INTR_X86_SSE2_COMINEQ_SD = 1501 -INTR_X86_SSE2_CVTDQ2PD = 1502 -INTR_X86_SSE2_CVTDQ2PS = 1503 -INTR_X86_SSE2_CVTPD2DQ = 1504 -INTR_X86_SSE2_CVTPD2PS = 1505 -INTR_X86_SSE2_CVTPS2DQ = 1506 -INTR_X86_SSE2_CVTPS2PD = 1507 -INTR_X86_SSE2_CVTSD2SI = 1508 -INTR_X86_SSE2_CVTSD2SI64 = 1509 -INTR_X86_SSE2_CVTSD2SS = 1510 -INTR_X86_SSE2_CVTSI2SD = 1511 -INTR_X86_SSE2_CVTSI642SD = 1512 -INTR_X86_SSE2_CVTSS2SD = 1513 -INTR_X86_SSE2_CVTTPD2DQ = 1514 -INTR_X86_SSE2_CVTTPS2DQ = 1515 -INTR_X86_SSE2_CVTTSD2SI = 1516 -INTR_X86_SSE2_CVTTSD2SI64 = 1517 -INTR_X86_SSE2_DIV_SD = 1518 -INTR_X86_SSE2_LFENCE = 1519 -INTR_X86_SSE2_MASKMOV_DQU = 1520 -INTR_X86_SSE2_MAX_PD = 1521 -INTR_X86_SSE2_MAX_SD = 1522 -INTR_X86_SSE2_MFENCE = 1523 -INTR_X86_SSE2_MIN_PD = 1524 -INTR_X86_SSE2_MIN_SD = 1525 -INTR_X86_SSE2_MOVMSK_PD = 1526 -INTR_X86_SSE2_MUL_SD = 1527 -INTR_X86_SSE2_PACKSSDW_128 = 1528 -INTR_X86_SSE2_PACKSSWB_128 = 1529 -INTR_X86_SSE2_PACKUSWB_128 = 1530 -INTR_X86_SSE2_PADDS_B = 1531 -INTR_X86_SSE2_PADDS_W = 1532 -INTR_X86_SSE2_PADDUS_B = 1533 -INTR_X86_SSE2_PADDUS_W = 1534 -INTR_X86_SSE2_PAVG_B = 1535 -INTR_X86_SSE2_PAVG_W = 1536 -INTR_X86_SSE2_PMADD_WD = 1537 -INTR_X86_SSE2_PMAXS_W = 1538 -INTR_X86_SSE2_PMAXU_B = 1539 -INTR_X86_SSE2_PMINS_W = 1540 -INTR_X86_SSE2_PMINU_B = 1541 -INTR_X86_SSE2_PMOVMSKB_128 = 1542 -INTR_X86_SSE2_PMULH_W = 1543 -INTR_X86_SSE2_PMULHU_W = 1544 -INTR_X86_SSE2_PMULU_DQ = 1545 -INTR_X86_SSE2_PSAD_BW = 1546 -INTR_X86_SSE2_PSLL_D = 1547 -INTR_X86_SSE2_PSLL_DQ = 1548 -INTR_X86_SSE2_PSLL_DQ_BS = 1549 -INTR_X86_SSE2_PSLL_Q = 1550 -INTR_X86_SSE2_PSLL_W = 1551 -INTR_X86_SSE2_PSLLI_D = 1552 -INTR_X86_SSE2_PSLLI_Q = 1553 -INTR_X86_SSE2_PSLLI_W = 1554 -INTR_X86_SSE2_PSRA_D = 1555 -INTR_X86_SSE2_PSRA_W = 1556 -INTR_X86_SSE2_PSRAI_D = 1557 -INTR_X86_SSE2_PSRAI_W = 1558 -INTR_X86_SSE2_PSRL_D = 1559 -INTR_X86_SSE2_PSRL_DQ = 1560 -INTR_X86_SSE2_PSRL_DQ_BS = 1561 -INTR_X86_SSE2_PSRL_Q = 1562 -INTR_X86_SSE2_PSRL_W = 1563 -INTR_X86_SSE2_PSRLI_D = 1564 -INTR_X86_SSE2_PSRLI_Q = 1565 -INTR_X86_SSE2_PSRLI_W = 1566 -INTR_X86_SSE2_PSUBS_B = 1567 -INTR_X86_SSE2_PSUBS_W = 1568 -INTR_X86_SSE2_PSUBUS_B = 1569 -INTR_X86_SSE2_PSUBUS_W = 1570 -INTR_X86_SSE2_SQRT_PD = 1571 -INTR_X86_SSE2_SQRT_SD = 1572 -INTR_X86_SSE2_STOREL_DQ = 1573 -INTR_X86_SSE2_STOREU_DQ = 1574 -INTR_X86_SSE2_STOREU_PD = 1575 -INTR_X86_SSE2_SUB_SD = 1576 -INTR_X86_SSE2_UCOMIEQ_SD = 1577 -INTR_X86_SSE2_UCOMIGE_SD = 1578 -INTR_X86_SSE2_UCOMIGT_SD = 1579 -INTR_X86_SSE2_UCOMILE_SD = 1580 -INTR_X86_SSE2_UCOMILT_SD = 1581 -INTR_X86_SSE2_UCOMINEQ_SD = 1582 -INTR_X86_SSE3_ADDSUB_PD = 1583 -INTR_X86_SSE3_ADDSUB_PS = 1584 -INTR_X86_SSE3_HADD_PD = 1585 -INTR_X86_SSE3_HADD_PS = 1586 -INTR_X86_SSE3_HSUB_PD = 1587 -INTR_X86_SSE3_HSUB_PS = 1588 -INTR_X86_SSE3_LDU_DQ = 1589 -INTR_X86_SSE3_MONITOR = 1590 -INTR_X86_SSE3_MWAIT = 1591 -INTR_X86_SSE41_BLENDPD = 1592 -INTR_X86_SSE41_BLENDPS = 1593 -INTR_X86_SSE41_BLENDVPD = 1594 -INTR_X86_SSE41_BLENDVPS = 1595 -INTR_X86_SSE41_DPPD = 1596 -INTR_X86_SSE41_DPPS = 1597 -INTR_X86_SSE41_EXTRACTPS = 1598 -INTR_X86_SSE41_INSERTPS = 1599 -INTR_X86_SSE41_MOVNTDQA = 1600 -INTR_X86_SSE41_MPSADBW = 1601 -INTR_X86_SSE41_PACKUSDW = 1602 -INTR_X86_SSE41_PBLENDVB = 1603 -INTR_X86_SSE41_PBLENDW = 1604 -INTR_X86_SSE41_PEXTRB = 1605 -INTR_X86_SSE41_PEXTRD = 1606 -INTR_X86_SSE41_PEXTRQ = 1607 -INTR_X86_SSE41_PHMINPOSUW = 1608 -INTR_X86_SSE41_PMAXSB = 1609 -INTR_X86_SSE41_PMAXSD = 1610 -INTR_X86_SSE41_PMAXUD = 1611 -INTR_X86_SSE41_PMAXUW = 1612 -INTR_X86_SSE41_PMINSB = 1613 -INTR_X86_SSE41_PMINSD = 1614 -INTR_X86_SSE41_PMINUD = 1615 -INTR_X86_SSE41_PMINUW = 1616 -INTR_X86_SSE41_PMOVSXBD = 1617 -INTR_X86_SSE41_PMOVSXBQ = 1618 -INTR_X86_SSE41_PMOVSXBW = 1619 -INTR_X86_SSE41_PMOVSXDQ = 1620 -INTR_X86_SSE41_PMOVSXWD = 1621 -INTR_X86_SSE41_PMOVSXWQ = 1622 -INTR_X86_SSE41_PMOVZXBD = 1623 -INTR_X86_SSE41_PMOVZXBQ = 1624 -INTR_X86_SSE41_PMOVZXBW = 1625 -INTR_X86_SSE41_PMOVZXDQ = 1626 -INTR_X86_SSE41_PMOVZXWD = 1627 -INTR_X86_SSE41_PMOVZXWQ = 1628 -INTR_X86_SSE41_PMULDQ = 1629 -INTR_X86_SSE41_PTESTC = 1630 -INTR_X86_SSE41_PTESTNZC = 1631 -INTR_X86_SSE41_PTESTZ = 1632 -INTR_X86_SSE41_ROUND_PD = 1633 -INTR_X86_SSE41_ROUND_PS = 1634 -INTR_X86_SSE41_ROUND_SD = 1635 -INTR_X86_SSE41_ROUND_SS = 1636 -INTR_X86_SSE42_CRC32_32_16 = 1637 -INTR_X86_SSE42_CRC32_32_32 = 1638 -INTR_X86_SSE42_CRC32_32_8 = 1639 -INTR_X86_SSE42_CRC32_64_64 = 1640 -INTR_X86_SSE42_CRC32_64_8 = 1641 -INTR_X86_SSE42_PCMPESTRI128 = 1642 -INTR_X86_SSE42_PCMPESTRIA128 = 1643 -INTR_X86_SSE42_PCMPESTRIC128 = 1644 -INTR_X86_SSE42_PCMPESTRIO128 = 1645 -INTR_X86_SSE42_PCMPESTRIS128 = 1646 -INTR_X86_SSE42_PCMPESTRIZ128 = 1647 -INTR_X86_SSE42_PCMPESTRM128 = 1648 -INTR_X86_SSE42_PCMPISTRI128 = 1649 -INTR_X86_SSE42_PCMPISTRIA128 = 1650 -INTR_X86_SSE42_PCMPISTRIC128 = 1651 -INTR_X86_SSE42_PCMPISTRIO128 = 1652 -INTR_X86_SSE42_PCMPISTRIS128 = 1653 -INTR_X86_SSE42_PCMPISTRIZ128 = 1654 -INTR_X86_SSE42_PCMPISTRM128 = 1655 -INTR_X86_SSE_ADD_SS = 1656 -INTR_X86_SSE_CMP_PS = 1657 -INTR_X86_SSE_CMP_SS = 1658 -INTR_X86_SSE_COMIEQ_SS = 1659 -INTR_X86_SSE_COMIGE_SS = 1660 -INTR_X86_SSE_COMIGT_SS = 1661 -INTR_X86_SSE_COMILE_SS = 1662 -INTR_X86_SSE_COMILT_SS = 1663 -INTR_X86_SSE_COMINEQ_SS = 1664 -INTR_X86_SSE_CVTPD2PI = 1665 -INTR_X86_SSE_CVTPI2PD = 1666 -INTR_X86_SSE_CVTPI2PS = 1667 -INTR_X86_SSE_CVTPS2PI = 1668 -INTR_X86_SSE_CVTSI2SS = 1669 -INTR_X86_SSE_CVTSI642SS = 1670 -INTR_X86_SSE_CVTSS2SI = 1671 -INTR_X86_SSE_CVTSS2SI64 = 1672 -INTR_X86_SSE_CVTTPD2PI = 1673 -INTR_X86_SSE_CVTTPS2PI = 1674 -INTR_X86_SSE_CVTTSS2SI = 1675 -INTR_X86_SSE_CVTTSS2SI64 = 1676 -INTR_X86_SSE_DIV_SS = 1677 -INTR_X86_SSE_LDMXCSR = 1678 -INTR_X86_SSE_MAX_PS = 1679 -INTR_X86_SSE_MAX_SS = 1680 -INTR_X86_SSE_MIN_PS = 1681 -INTR_X86_SSE_MIN_SS = 1682 -INTR_X86_SSE_MOVMSK_PS = 1683 -INTR_X86_SSE_MUL_SS = 1684 -INTR_X86_SSE_PSHUF_W = 1685 -INTR_X86_SSE_RCP_PS = 1686 -INTR_X86_SSE_RCP_SS = 1687 -INTR_X86_SSE_RSQRT_PS = 1688 -INTR_X86_SSE_RSQRT_SS = 1689 -INTR_X86_SSE_SFENCE = 1690 -INTR_X86_SSE_SQRT_PS = 1691 -INTR_X86_SSE_SQRT_SS = 1692 -INTR_X86_SSE_STMXCSR = 1693 -INTR_X86_SSE_STOREU_PS = 1694 -INTR_X86_SSE_SUB_SS = 1695 -INTR_X86_SSE_UCOMIEQ_SS = 1696 -INTR_X86_SSE_UCOMIGE_SS = 1697 -INTR_X86_SSE_UCOMIGT_SS = 1698 -INTR_X86_SSE_UCOMILE_SS = 1699 -INTR_X86_SSE_UCOMILT_SS = 1700 -INTR_X86_SSE_UCOMINEQ_SS = 1701 -INTR_X86_SSSE3_PABS_B = 1702 -INTR_X86_SSSE3_PABS_B_128 = 1703 -INTR_X86_SSSE3_PABS_D = 1704 -INTR_X86_SSSE3_PABS_D_128 = 1705 -INTR_X86_SSSE3_PABS_W = 1706 -INTR_X86_SSSE3_PABS_W_128 = 1707 -INTR_X86_SSSE3_PHADD_D = 1708 -INTR_X86_SSSE3_PHADD_D_128 = 1709 -INTR_X86_SSSE3_PHADD_SW = 1710 -INTR_X86_SSSE3_PHADD_SW_128 = 1711 -INTR_X86_SSSE3_PHADD_W = 1712 -INTR_X86_SSSE3_PHADD_W_128 = 1713 -INTR_X86_SSSE3_PHSUB_D = 1714 -INTR_X86_SSSE3_PHSUB_D_128 = 1715 -INTR_X86_SSSE3_PHSUB_SW = 1716 -INTR_X86_SSSE3_PHSUB_SW_128 = 1717 -INTR_X86_SSSE3_PHSUB_W = 1718 -INTR_X86_SSSE3_PHSUB_W_128 = 1719 -INTR_X86_SSSE3_PMADD_UB_SW = 1720 -INTR_X86_SSSE3_PMADD_UB_SW_128 = 1721 -INTR_X86_SSSE3_PMUL_HR_SW = 1722 -INTR_X86_SSSE3_PMUL_HR_SW_128 = 1723 -INTR_X86_SSSE3_PSHUF_B = 1724 -INTR_X86_SSSE3_PSHUF_B_128 = 1725 -INTR_X86_SSSE3_PSIGN_B = 1726 -INTR_X86_SSSE3_PSIGN_B_128 = 1727 -INTR_X86_SSSE3_PSIGN_D = 1728 -INTR_X86_SSSE3_PSIGN_D_128 = 1729 -INTR_X86_SSSE3_PSIGN_W = 1730 -INTR_X86_SSSE3_PSIGN_W_128 = 1731 -INTR_X86_VCVTPH2PS_128 = 1732 -INTR_X86_VCVTPH2PS_256 = 1733 -INTR_X86_VCVTPS2PH_128 = 1734 -INTR_X86_VCVTPS2PH_256 = 1735 -INTR_X86_WRFSBASE_32 = 1736 -INTR_X86_WRFSBASE_64 = 1737 -INTR_X86_WRGSBASE_32 = 1738 -INTR_X86_WRGSBASE_64 = 1739 -INTR_X86_XOP_VFRCZ_PD = 1740 -INTR_X86_XOP_VFRCZ_PD_256 = 1741 -INTR_X86_XOP_VFRCZ_PS = 1742 -INTR_X86_XOP_VFRCZ_PS_256 = 1743 -INTR_X86_XOP_VFRCZ_SD = 1744 -INTR_X86_XOP_VFRCZ_SS = 1745 -INTR_X86_XOP_VPCMOV = 1746 -INTR_X86_XOP_VPCMOV_256 = 1747 -INTR_X86_XOP_VPCOMEQB = 1748 -INTR_X86_XOP_VPCOMEQD = 1749 -INTR_X86_XOP_VPCOMEQQ = 1750 -INTR_X86_XOP_VPCOMEQUB = 1751 -INTR_X86_XOP_VPCOMEQUD = 1752 -INTR_X86_XOP_VPCOMEQUQ = 1753 -INTR_X86_XOP_VPCOMEQUW = 1754 -INTR_X86_XOP_VPCOMEQW = 1755 -INTR_X86_XOP_VPCOMFALSEB = 1756 -INTR_X86_XOP_VPCOMFALSED = 1757 -INTR_X86_XOP_VPCOMFALSEQ = 1758 -INTR_X86_XOP_VPCOMFALSEUB = 1759 -INTR_X86_XOP_VPCOMFALSEUD = 1760 -INTR_X86_XOP_VPCOMFALSEUQ = 1761 -INTR_X86_XOP_VPCOMFALSEUW = 1762 -INTR_X86_XOP_VPCOMFALSEW = 1763 -INTR_X86_XOP_VPCOMGEB = 1764 -INTR_X86_XOP_VPCOMGED = 1765 -INTR_X86_XOP_VPCOMGEQ = 1766 -INTR_X86_XOP_VPCOMGEUB = 1767 -INTR_X86_XOP_VPCOMGEUD = 1768 -INTR_X86_XOP_VPCOMGEUQ = 1769 -INTR_X86_XOP_VPCOMGEUW = 1770 -INTR_X86_XOP_VPCOMGEW = 1771 -INTR_X86_XOP_VPCOMGTB = 1772 -INTR_X86_XOP_VPCOMGTD = 1773 -INTR_X86_XOP_VPCOMGTQ = 1774 -INTR_X86_XOP_VPCOMGTUB = 1775 -INTR_X86_XOP_VPCOMGTUD = 1776 -INTR_X86_XOP_VPCOMGTUQ = 1777 -INTR_X86_XOP_VPCOMGTUW = 1778 -INTR_X86_XOP_VPCOMGTW = 1779 -INTR_X86_XOP_VPCOMLEB = 1780 -INTR_X86_XOP_VPCOMLED = 1781 -INTR_X86_XOP_VPCOMLEQ = 1782 -INTR_X86_XOP_VPCOMLEUB = 1783 -INTR_X86_XOP_VPCOMLEUD = 1784 -INTR_X86_XOP_VPCOMLEUQ = 1785 -INTR_X86_XOP_VPCOMLEUW = 1786 -INTR_X86_XOP_VPCOMLEW = 1787 -INTR_X86_XOP_VPCOMLTB = 1788 -INTR_X86_XOP_VPCOMLTD = 1789 -INTR_X86_XOP_VPCOMLTQ = 1790 -INTR_X86_XOP_VPCOMLTUB = 1791 -INTR_X86_XOP_VPCOMLTUD = 1792 -INTR_X86_XOP_VPCOMLTUQ = 1793 -INTR_X86_XOP_VPCOMLTUW = 1794 -INTR_X86_XOP_VPCOMLTW = 1795 -INTR_X86_XOP_VPCOMNEB = 1796 -INTR_X86_XOP_VPCOMNED = 1797 -INTR_X86_XOP_VPCOMNEQ = 1798 -INTR_X86_XOP_VPCOMNEUB = 1799 -INTR_X86_XOP_VPCOMNEUD = 1800 -INTR_X86_XOP_VPCOMNEUQ = 1801 -INTR_X86_XOP_VPCOMNEUW = 1802 -INTR_X86_XOP_VPCOMNEW = 1803 -INTR_X86_XOP_VPCOMTRUEB = 1804 -INTR_X86_XOP_VPCOMTRUED = 1805 -INTR_X86_XOP_VPCOMTRUEQ = 1806 -INTR_X86_XOP_VPCOMTRUEUB = 1807 -INTR_X86_XOP_VPCOMTRUEUD = 1808 -INTR_X86_XOP_VPCOMTRUEUQ = 1809 -INTR_X86_XOP_VPCOMTRUEUW = 1810 -INTR_X86_XOP_VPCOMTRUEW = 1811 -INTR_X86_XOP_VPERMIL2PD = 1812 -INTR_X86_XOP_VPERMIL2PD_256 = 1813 -INTR_X86_XOP_VPERMIL2PS = 1814 -INTR_X86_XOP_VPERMIL2PS_256 = 1815 -INTR_X86_XOP_VPHADDBD = 1816 -INTR_X86_XOP_VPHADDBQ = 1817 -INTR_X86_XOP_VPHADDBW = 1818 -INTR_X86_XOP_VPHADDDQ = 1819 -INTR_X86_XOP_VPHADDUBD = 1820 -INTR_X86_XOP_VPHADDUBQ = 1821 -INTR_X86_XOP_VPHADDUBW = 1822 -INTR_X86_XOP_VPHADDUDQ = 1823 -INTR_X86_XOP_VPHADDUWD = 1824 -INTR_X86_XOP_VPHADDUWQ = 1825 -INTR_X86_XOP_VPHADDWD = 1826 -INTR_X86_XOP_VPHADDWQ = 1827 -INTR_X86_XOP_VPHSUBBW = 1828 -INTR_X86_XOP_VPHSUBDQ = 1829 -INTR_X86_XOP_VPHSUBWD = 1830 -INTR_X86_XOP_VPMACSDD = 1831 -INTR_X86_XOP_VPMACSDQH = 1832 -INTR_X86_XOP_VPMACSDQL = 1833 -INTR_X86_XOP_VPMACSSDD = 1834 -INTR_X86_XOP_VPMACSSDQH = 1835 -INTR_X86_XOP_VPMACSSDQL = 1836 -INTR_X86_XOP_VPMACSSWD = 1837 -INTR_X86_XOP_VPMACSSWW = 1838 -INTR_X86_XOP_VPMACSWD = 1839 -INTR_X86_XOP_VPMACSWW = 1840 -INTR_X86_XOP_VPMADCSSWD = 1841 -INTR_X86_XOP_VPMADCSWD = 1842 -INTR_X86_XOP_VPPERM = 1843 -INTR_X86_XOP_VPROTB = 1844 -INTR_X86_XOP_VPROTD = 1845 -INTR_X86_XOP_VPROTQ = 1846 -INTR_X86_XOP_VPROTW = 1847 -INTR_X86_XOP_VPSHAB = 1848 -INTR_X86_XOP_VPSHAD = 1849 -INTR_X86_XOP_VPSHAQ = 1850 -INTR_X86_XOP_VPSHAW = 1851 -INTR_X86_XOP_VPSHLB = 1852 -INTR_X86_XOP_VPSHLD = 1853 -INTR_X86_XOP_VPSHLQ = 1854 -INTR_X86_XOP_VPSHLW = 1855 -INTR_XCORE_BITREV = 1856 -INTR_XCORE_CHECKEVENT = 1857 -INTR_XCORE_CHKCT = 1858 -INTR_XCORE_CLRE = 1859 -INTR_XCORE_CLRSR = 1860 -INTR_XCORE_CRC32 = 1861 -INTR_XCORE_CRC8 = 1862 -INTR_XCORE_EEU = 1863 -INTR_XCORE_ENDIN = 1864 -INTR_XCORE_FREER = 1865 -INTR_XCORE_GETED = 1866 -INTR_XCORE_GETET = 1867 -INTR_XCORE_GETID = 1868 -INTR_XCORE_GETPS = 1869 -INTR_XCORE_GETR = 1870 -INTR_XCORE_GETST = 1871 -INTR_XCORE_GETTS = 1872 -INTR_XCORE_IN = 1873 -INTR_XCORE_INCT = 1874 -INTR_XCORE_INITCP = 1875 -INTR_XCORE_INITDP = 1876 -INTR_XCORE_INITLR = 1877 -INTR_XCORE_INITPC = 1878 -INTR_XCORE_INITSP = 1879 -INTR_XCORE_INSHR = 1880 -INTR_XCORE_INT = 1881 -INTR_XCORE_MJOIN = 1882 -INTR_XCORE_MSYNC = 1883 -INTR_XCORE_OUT = 1884 -INTR_XCORE_OUTCT = 1885 -INTR_XCORE_OUTSHR = 1886 -INTR_XCORE_OUTT = 1887 -INTR_XCORE_PEEK = 1888 -INTR_XCORE_SETC = 1889 -INTR_XCORE_SETCLK = 1890 -INTR_XCORE_SETD = 1891 -INTR_XCORE_SETEV = 1892 -INTR_XCORE_SETPS = 1893 -INTR_XCORE_SETPSC = 1894 -INTR_XCORE_SETPT = 1895 -INTR_XCORE_SETRDY = 1896 -INTR_XCORE_SETSR = 1897 -INTR_XCORE_SETTW = 1898 -INTR_XCORE_SETV = 1899 -INTR_XCORE_SEXT = 1900 -INTR_XCORE_SSYNC = 1901 -INTR_XCORE_SYNCR = 1902 -INTR_XCORE_TESTCT = 1903 -INTR_XCORE_TESTWCT = 1904 -INTR_XCORE_WAITEVENT = 1905 -INTR_XCORE_ZEXT = 1906 - diff --git a/llvm/core.py b/llvm/core.py index 0560f5b..623960a 100644 --- a/llvm/core.py +++ b/llvm/core.py @@ -2155,8 +2155,19 @@ if _core.LLVMInitializeNativeTargetAsmPrinter(): # should user trigger the initialization? raise llvm.LLVMException("No native asm printer!?") -if True: # use PTX - _core.LLVMInitializePTXTarget() - _core.LLVMInitializePTXTargetInfo() - _core.LLVMInitializePTXTargetMC() - _core.LLVMInitializePTXAsmPrinter() + +HAS_PTX = HAS_NVPTX = False +if True: # use PTX? + try: + _core.LLVMInitializePTXTarget() + _core.LLVMInitializePTXTargetInfo() + _core.LLVMInitializePTXTargetMC() + _core.LLVMInitializePTXAsmPrinter() + HAS_PTX = True + except AttributeError: + _core.LLVMInitializeNVPTXTarget() + _core.LLVMInitializeNVPTXTargetInfo() + _core.LLVMInitializeNVPTXTargetMC() + _core.LLVMInitializeNVPTXAsmPrinter() + HAS_NVPTX = True + diff --git a/llvm/extra.cpp b/llvm/extra.cpp index 500367f..64e2680 100644 --- a/llvm/extra.cpp +++ b/llvm/extra.cpp @@ -893,6 +893,7 @@ LLVMModuleRef LLVMGetModuleFromBitcode(const char *bitcode, unsigned bclen, return wrap(modulep); } +#if LLVM_VERSION_MAJOR <= 3 && LLVM_VERSION_MINOR < 2 unsigned LLVMLinkModules(LLVMModuleRef dest, LLVMModuleRef src, unsigned int mode, char **out) { @@ -909,6 +910,7 @@ unsigned LLVMLinkModules(LLVMModuleRef dest, LLVMModuleRef src, unsigned int mod return 1; } +#endif unsigned char *LLVMGetBitcodeFromModule(LLVMModuleRef module, unsigned *lenp) { diff --git a/llvm/extra.h b/llvm/extra.h index a335a58..3ff0858 100644 --- a/llvm/extra.h +++ b/llvm/extra.h @@ -37,10 +37,20 @@ #ifndef LLVM_PY_EXTRA_H #define LLVM_PY_EXTRA_H +// select PTX or NVPTX + +#if LLVM_VERSION_MAJOR >= 3 && LLVM_VERSION_MINOR >= 2 + #define LLVM_HAS_NVPTX 1 +#else + #define LLVM_HAS_NVPTX 0 +#endif + + #include "llvm-c/Transforms/PassManagerBuilder.h" #include "llvm_c_extra.h" + #ifdef __cplusplus extern "C" { #endif @@ -381,12 +391,13 @@ LLVMModuleRef LLVMGetModuleFromAssembly(const char *asmtxt, char **out); LLVMModuleRef LLVMGetModuleFromBitcode(const char *bc, unsigned bclen, char **out); +#if LLVM_VERSION_MAJOR <= 3 && LLVM_VERSION_MINOR < 2 /* Wraps llvm::Linker::LinkModules(). Returns 0 on failure (with errmsg * filled in) and 1 on success. Dispose error message after use with * LLVMDisposeMessage(). */ unsigned LLVMLinkModules(LLVMModuleRef dest, LLVMModuleRef src, unsigned int, char **errmsg); - +#endif /* Returns pointer to a heap-allocated block of `*len' bytes containing bit code * for the given module. NULL on error. */ unsigned char *LLVMGetBitcodeFromModule(LLVMModuleRef module, unsigned *len); diff --git a/setup.py b/setup.py index f9d3e10..9d455d3 100755 --- a/setup.py +++ b/setup.py @@ -29,7 +29,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -import sys, os +import sys, os, re from distutils.core import setup, Extension LLVM_PY_VERSION = '0.8.2' @@ -72,6 +72,20 @@ def get_llvm_config(): return (lc, True) +def get_version(llvm_config): + # get version number; treat it as fixed point + re_version = re.compile(r'(\d+)\.(\d+)') + raw = _run(llvm_config + ' --version') + major, minor = map(int, re_version.match(raw).groups()) + return major, minor + +def auto_intrinsic_gen(llvm_config, incdir): + # let's do auto intrinsic generation + print("Generate intrinsic IDs") + from tools import intrgen + path = "%s/llvm/Intrinsics.gen" % incdir + with open('llvm/_intrinsic_ids.py', 'w') as fout: + intrgen.gen(path, fout) def call_setup(llvm_config): @@ -79,7 +93,26 @@ def call_setup(llvm_config): libdir = _run(llvm_config + ' --libdir') ldflags = _run(llvm_config + ' --ldflags') - ptx_components = ['ptx', 'ptxasmprinter', 'ptxcodegen', 'ptxdesc', 'ptxinfo'] + llvm_version = get_version(llvm_config) + print('LLVM version = %d.%d' % llvm_version) + + auto_intrinsic_gen(llvm_config, incdir) + + if llvm_version <= (3, 1): # select between PTX & NVPTX + print('Using PTX') + ptx_components = ['ptx', + 'ptxasmprinter', + 'ptxcodegen', + 'ptxdesc', + 'ptxinfo'] + else: + print('Using NVPTX') + ptx_components = ['nvptx', + 'nvptxasmprinter', + 'nvptxcodegen', + 'nvptxdesc', + 'nvptxinfo'] + libs_core, objs_core = get_libs_and_objs(llvm_config, ['core', 'analysis', 'scalaropts', 'executionengine', diff --git a/test/targetmachines.py b/test/targetmachines.py index 9ce85dd..d11df50 100644 --- a/test/targetmachines.py +++ b/test/targetmachines.py @@ -19,17 +19,22 @@ class TestTargetMachines(unittest.TestCase): self.assertIn('foo', tm.emit_assembly(m).decode('utf-8')) def test_ptx(self): + if HAS_PTX: + arch = 'ptx64' + elif HAS_NVPTX: + arch = 'nvptx64' + else: + return # skip this test m, func = self._build_module() func.calling_convention = CC_PTX_KERNEL # set calling conv - ptxtm = TargetMachine.lookup(arch='ptx64', cpu='compute_20', - features='-double') + ptxtm = TargetMachine.lookup(arch=arch, cpu='compute_20') self.assertTrue(ptxtm.triple) self.assertTrue(ptxtm.cpu) - self.assertTrue(ptxtm.feature_string) ptxasm = ptxtm.emit_assembly(m).decode('utf-8') self.assertIn('foo', ptxasm) - self.assertIn('map_f64_to_f32', ptxasm) - self.assertIn('compute_10', ptxasm) + if HAS_NVPTX: + self.assertIn('.address_size 64', ptxasm) + self.assertIn('compute_20', ptxasm) def _build_module(self): m = Module.new('TestTargetMachines') diff --git a/tools/__init__.py b/tools/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/tools/intrgen.py b/tools/intrgen.py index 8f46192..c22da25 100755 --- a/tools/intrgen.py +++ b/tools/intrgen.py @@ -6,7 +6,7 @@ import sys -def gen(f): +def gen(f, out=sys.stdout): intr = [] maxw = 0 flag = False @@ -26,7 +26,8 @@ def gen(f): idx = 1 for i in intr: s = 'INTR_' + i.upper() - print('%s = %d' % (s.ljust(maxw), idx)) + out.write('%s = %d\n' % (s.ljust(maxw), idx)) idx += 1 -gen(sys.argv[1]) +if __name__ == '__main__': + gen(sys.argv[1])