As was present vividly breaks LLVM IR constraints on SSA and basic-blocks: same var being assigned twice, no control transfer at the end of basic block. Compare with the original: http://www.mdevan.org/llvm-py/kaleidoscope/PythonLangImpl5.html |
||
|---|---|---|
| .. | ||
| doc | ||
| conf.py | ||
| index.rst | ||