add or1k (OpenRISC 1000) architecture port

With the exception of a fenv implementation, the port is fully featured.
The port has been tested in or1ksim, the golden reference functional
simulator for OpenRISC 1000.
It passes all libc-test tests (except the math tests that
requires a fenv implementation).

The port assumes an or1k implementation that has support for
atomic instructions (l.lwa/l.swa).

Although it passes all the libc-test tests, the port is still
in an experimental state, and has yet experienced very little
'real-world' use.

src/thread/or1k/__set_thread_area.s

@@ -0,0 +1,6 @@
+.global __set_thread_area
+.type   __set_thread_area,@function
+__set_thread_area:
+	l.ori	r10, r3, 0
+	l.jr	r9
+	 l.ori	r11, r0, 0

src/thread/or1k/__unmapself.s

@@ -0,0 +1,8 @@
+.global __unmapself
+.type   __unmapself,@function
+__unmapself:
+	l.ori	r11, r0, 215 /* __NR_munmap */
+	l.sys	1
+	l.ori	r3, r0, 0
+	l.ori	r11, r0, 93 /* __NR_exit */
+	l.sys	1

src/thread/or1k/clone.s

@@ -0,0 +1,30 @@
+/* int clone(fn, stack, flags, arg, ptid, tls, ctid)
+ *           r3  r4     r5     r6   sp+0  sp+4 sp+8
+ * sys_clone(flags, stack, ptid, ctid, tls)
+ */
+.global __clone
+.type   __clone,@function
+__clone:
+	l.addi	r4, r4, -8
+	l.sw	0(r4), r3
+	l.sw	4(r4), r6
+	/* (fn, st, fl, ar, pt, tl, ct) => (fl, st, pt, ct, tl) */
+	l.ori	r3, r5, 0
+	l.lwz	r5, 0(r1)
+	l.lwz	r6, 8(r1)
+	l.lwz	r7, 4(r1)
+	l.ori	r11, r0, 220 /* __NR_clone */
+	l.sys	1
+
+	l.sfeqi	r11, 0
+	l.bf	1f
+	 l.nop
+	l.jr	r9
+	 l.nop
+
+1:	l.lwz	r11, 0(r1)
+	l.jalr	r11
+	 l.lwz	r3, 4(r1)
+
+	l.ori	r11, r0, 93 /* __NR_exit */
+	l.sys	1

src/thread/or1k/syscall_cp.s

@@ -0,0 +1,20 @@
+.global __syscall_cp_asm
+.type   __syscall_cp_asm,@function
+__syscall_cp_asm:
+.global __cp_begin
+__cp_begin:
+	l.lwz	r3, 0(r3)
+	l.sfeqi	r3, 0
+	l.bnf	plt(__cancel)
+	 l.ori	r11, r4, 0
+	l.ori	r3, r5, 0
+	l.ori	r4, r6, 0
+	l.ori	r5, r7, 0
+	l.ori	r6, r8, 0
+	l.lwz	r7, 0(r1)
+	l.lwz	r8, 4(r1)
+	l.sys	1
+.global __cp_end
+__cp_end:
+	l.jr	r9
+	 l.nop