add nofpu subarchs to the sh arch, and properly detect compiler's fpu config

src/fenv/sh-nofpu/fenv.sub

@@ -0,0 +1 @@
+../fenv.c

src/fenv/sheb-nofpu/fenv.sub

@@ -0,0 +1 @@
+../fenv.c

src/setjmp/sh-nofpu/longjmp.s

@@ -0,0 +1,22 @@
+.global _longjmp
+.global longjmp
+.type   _longjmp, @function
+.type   longjmp,  @function
+_longjmp:
+longjmp:
+	mov.l  @r4+, r8
+	mov.l  @r4+, r9
+	mov.l  @r4+, r10
+	mov.l  @r4+, r11
+	mov.l  @r4+, r12
+	mov.l  @r4+, r13
+	mov.l  @r4+, r14
+	mov.l  @r4+, r15
+	lds.l  @r4+, pr
+
+	tst  r5, r5
+	movt r0
+	add  r5, r0
+
+	rts
+	 nop

src/setjmp/sh-nofpu/longjmp.sub

@@ -0,0 +1 @@
+longjmp.s

src/setjmp/sh-nofpu/setjmp.s

@@ -0,0 +1,21 @@
+.global __setjmp
+.global _setjmp
+.global setjmp
+.type   __setjmp, @function
+.type   _setjmp,  @function
+.type   setjmp,   @function
+__setjmp:
+_setjmp:
+setjmp:
+	add   #36, r4
+	sts.l  pr,   @-r4
+	mov.l  r15   @-r4
+	mov.l  r14,  @-r4
+	mov.l  r13,  @-r4
+	mov.l  r12,  @-r4
+	mov.l  r11,  @-r4
+	mov.l  r10,  @-r4
+	mov.l  r9,   @-r4
+	mov.l  r8,   @-r4
+	rts
+	 mov  #0, r0

src/setjmp/sh-nofpu/setjmp.sub

@@ -0,0 +1 @@
+setjmp.s

src/setjmp/sheb-nofpu/longjmp.sub

@@ -0,0 +1 @@
+../sh-nofpu/longjmp.s

src/setjmp/sheb-nofpu/setjmp.sub

@@ -0,0 +1 @@
+../sh-nofpu/setjmp.s