Gate controller pairing behind BOOTSEL

tests/bootsel_native_stubs/hardware/gpio.h

@@ -0,0 +1,27 @@
+#pragma once
+
+#include <cstdint>
+
+using io_rw_32 = volatile uint32_t;
+
+enum gpio_override {
+    GPIO_OVERRIDE_NORMAL = 0,
+    GPIO_OVERRIDE_LOW = 2,
+};
+
+void bootsel_test_masked_write(io_rw_32* address, uint32_t values,
+                               uint32_t mask);
+
+inline void hw_write_masked(io_rw_32* address, uint32_t values,
+                            uint32_t mask) {
+    *address = (*address & ~mask) | (values & mask);
+    bootsel_test_masked_write(address, values, mask);
+}
+
+#if PICO_RP2350
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB 14u
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS 0x0000c000u
+#else
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB 12u
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS 0x00003000u
+#endif

tests/bootsel_native_stubs/hardware/regs/sio.h

@@ -0,0 +1,3 @@
+#pragma once
+
+#define SIO_GPIO_HI_IN_QSPI_CSN_BITS 0x08000000u

tests/bootsel_native_stubs/hardware/structs/ioqspi.h

@@ -0,0 +1,14 @@
+#pragma once
+
+#include "hardware/gpio.h"
+
+struct ioqspi_status_ctrl_hw_t {
+    io_rw_32 status;
+    io_rw_32 ctrl;
+};
+
+struct ioqspi_hw_t {
+    ioqspi_status_ctrl_hw_t io[6];
+};
+
+extern ioqspi_hw_t* ioqspi_hw;

tests/bootsel_native_stubs/hardware/structs/sio.h

@@ -0,0 +1,10 @@
+#pragma once
+
+#include <cstdint>
+
+struct sio_hw_t {
+    volatile uint32_t gpio_in;
+    volatile uint32_t gpio_hi_in;
+};
+
+extern sio_hw_t* sio_hw;